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| author | Markus Armbruster <armbru@redhat.com> | 2020-06-30 11:03:42 +0200 |
|---|---|---|
| committer | Markus Armbruster <armbru@redhat.com> | 2020-07-02 06:25:29 +0200 |
| commit | cbe3a8c582f964a222b64bce02a0a3ae22dc0efd (patch) | |
| tree | a3e30cf1c9621aa758c0aa06720e8a01048a19b7 /hw/mips/cps.c | |
| parent | c24d97168a3ec92d4d624bb463214e449be0a42d (diff) | |
| download | focaccia-qemu-cbe3a8c582f964a222b64bce02a0a3ae22dc0efd.tar.gz focaccia-qemu-cbe3a8c582f964a222b64bce02a0a3ae22dc0efd.zip | |
riscv/sifive_u: Fix sifive_u_soc_realize() error API violations
The Error ** argument must be NULL, &error_abort, &error_fatal, or a pointer to a variable containing NULL. Passing an argument of the latter kind twice without clearing it in between is wrong: if the first call sets an error, it no longer points to NULL for the second call. sifive_u_soc_realize() is wrong that way: it passes &err to sysbus_realize() four times before checking it. Harmless, because the first three can't actually fail (I think). Fix by checking for failure right away. Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: qemu-riscv@nongnu.org Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200630090351.1247703-18-armbru@redhat.com>
Diffstat (limited to 'hw/mips/cps.c')
0 files changed, 0 insertions, 0 deletions