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| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-01-24 01:47:51 +0000 |
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| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-01-24 01:47:51 +0000 |
| commit | 4de9b249d37c1b382cc3e5a21fad1b4a11cec2fa (patch) | |
| tree | 3991d58b09108b5c18a4388b2c2a8b6cb8f57142 /hw/mips_r4k.c | |
| parent | 30c4bbace19e802979009cc5c16fb4e14dc6bda6 (diff) | |
| download | focaccia-qemu-4de9b249d37c1b382cc3e5a21fad1b4a11cec2fa.tar.gz focaccia-qemu-4de9b249d37c1b382cc3e5a21fad1b4a11cec2fa.zip | |
Reworking MIPS interrupt handling, by Aurelien Jarno.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2350 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/mips_r4k.c')
| -rw-r--r-- | hw/mips_r4k.c | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c index ffed67c2a5..5fa5b76a68 100644 --- a/hw/mips_r4k.c +++ b/hw/mips_r4k.c @@ -38,14 +38,7 @@ static PITState *pit; /* PIT i8254 */ /*The PIC is attached to the MIPS CPU INT0 pin */ static void pic_irq_request(void *opaque, int level) { - CPUState *env = first_cpu; - if (level) { - env->CP0_Cause |= 0x00000400; - cpu_interrupt(env, CPU_INTERRUPT_HARD); - } else { - env->CP0_Cause &= ~0x00000400; - cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); - } + cpu_mips_irq_request(opaque, 2, level); } static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, |