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| author | Weiwei Li <liweiwei@iscas.ac.cn> | 2022-04-23 10:35:08 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-04-29 10:47:45 +1000 |
| commit | 77442380ecbe3b3c092c2a48dbfe8286336e7e78 (patch) | |
| tree | 3cda54192edfe4bc0bd0bcd87a0537102ff5006b /hw/misc/arm_integrator_debug.c | |
| parent | 0976083d1be23d72b9a4857f6d8c3d86b5f11efa (diff) | |
| download | focaccia-qemu-77442380ecbe3b3c092c2a48dbfe8286336e7e78.tar.gz focaccia-qemu-77442380ecbe3b3c092c2a48dbfe8286336e7e78.zip | |
target/riscv: rvk: add CSR support for Zkr
- add SEED CSR which must be accessed with a read-write instruction: A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI with uimm=0 will raise an illegal instruction exception. - add USEED, SSEED fields for MSECCFG CSR Co-authored-by: Ruibo Lu <luruibo2000@163.com> Co-authored-by: Zewen Ye <lustrew@foxmail.com> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220423023510.30794-13-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/misc/arm_integrator_debug.c')
0 files changed, 0 insertions, 0 deletions