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| author | Cédric Le Goater <clg@kaod.org> | 2019-11-19 15:11:57 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-12-16 10:46:34 +0000 |
| commit | 95b56e173e20267778965a2bfd1afd517f7342c4 (patch) | |
| tree | cea88eb3f1defdab586cdae5d3eb8c24cbf5e365 /hw/misc/aspeed_scu.c | |
| parent | aab90b1cacb8b808d4f00c9709595c50b9d1f7a2 (diff) | |
| download | focaccia-qemu-95b56e173e20267778965a2bfd1afd517f7342c4.tar.gz focaccia-qemu-95b56e173e20267778965a2bfd1afd517f7342c4.zip | |
aspeed: Add a DRAM memory region at the SoC level
Currently, we link the DRAM memory region to the FMC model (for DMAs) through a property alias at the SoC level. The I2C model will need a similar region for DMA support, add a DRAM region property at the SoC level for both model to use. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 20191119141211.25716-4-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/misc/aspeed_scu.c')
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