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| author | Joel Stanley <joel@jms.id.au> | 2018-08-16 14:05:29 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-08-16 14:29:58 +0100 |
| commit | a7b4569a4dddf0255d29ec56045c65f9bcb60919 (patch) | |
| tree | 04d68ffd50b8a97b664bbd5ef2b9d4cf97a75e65 /hw/misc/aspeed_sdmc.c | |
| parent | 33883ce840b291f4f5767aea911b56acae8dfb66 (diff) | |
| download | focaccia-qemu-a7b4569a4dddf0255d29ec56045c65f9bcb60919.tar.gz focaccia-qemu-a7b4569a4dddf0255d29ec56045c65f9bcb60919.zip | |
aspeed_sdmc: Handle ECC training
This is required to ensure u-boot SDRAM training completes. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20180807075757.7242-6-joel@jms.id.au Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/misc/aspeed_sdmc.c')
| -rw-r--r-- | hw/misc/aspeed_sdmc.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index 522e01ef8c..89de3138af 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/misc/aspeed_sdmc.c @@ -27,6 +27,10 @@ #define R_STATUS1 (0x60 / 4) #define PHY_BUSY_STATE BIT(0) +#define R_ECC_TEST_CTRL (0x70 / 4) +#define ECC_TEST_FINISHED BIT(12) +#define ECC_TEST_FAIL BIT(13) + /* * Configuration register Ox4 (for Aspeed AST2400 SOC) * @@ -148,6 +152,11 @@ static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data, /* Will never return 'busy' */ data &= ~PHY_BUSY_STATE; break; + case R_ECC_TEST_CTRL: + /* Always done, always happy */ + data |= ECC_TEST_FINISHED; + data &= ~ECC_TEST_FAIL; + break; default: break; } |