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authorCédric Le Goater <clg@kaod.org>2016-09-22 18:13:06 +0100
committerPeter Maydell <peter.maydell@linaro.org>2016-09-22 18:13:06 +0100
commitc6c7cfb01a00be0553f6694bbe71d45fc5e068c8 (patch)
tree3883b3fe92e2773ad78ba74a0910b33c08bb1944 /hw/misc/aspeed_sdmc.c
parentb2fd45458d294e0a8a7c559881788d8642958bb7 (diff)
downloadfocaccia-qemu-c6c7cfb01a00be0553f6694bbe71d45fc5e068c8.tar.gz
focaccia-qemu-c6c7cfb01a00be0553f6694bbe71d45fc5e068c8.zip
aspeed: add a ram_size property to the memory controller
Configure the size of the RAM of the SOC using a property to propagate
the value down to the memory controller from the board level.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Message-id: 1473438177-26079-14-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/misc/aspeed_sdmc.c')
-rw-r--r--hw/misc/aspeed_sdmc.c23
1 files changed, 13 insertions, 10 deletions
diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c
index 20bcdb52c4..8830dc084c 100644
--- a/hw/misc/aspeed_sdmc.c
+++ b/hw/misc/aspeed_sdmc.c
@@ -140,9 +140,9 @@ static const MemoryRegionOps aspeed_sdmc_ops = {
     .valid.max_access_size = 4,
 };
 
-static int ast2400_rambits(void)
+static int ast2400_rambits(AspeedSDMCState *s)
 {
-    switch (ram_size >> 20) {
+    switch (s->ram_size >> 20) {
     case 64:
         return ASPEED_SDMC_DRAM_64MB;
     case 128:
@@ -156,14 +156,15 @@ static int ast2400_rambits(void)
     }
 
     /* use a common default */
-    error_report("warning: Invalid RAM size 0x" RAM_ADDR_FMT
-                 ". Using default 256M", ram_size);
+    error_report("warning: Invalid RAM size 0x%" PRIx64
+                 ". Using default 256M", s->ram_size);
+    s->ram_size = 256 << 20;
     return ASPEED_SDMC_DRAM_256MB;
 }
 
-static int ast2500_rambits(void)
+static int ast2500_rambits(AspeedSDMCState *s)
 {
-    switch (ram_size >> 20) {
+    switch (s->ram_size >> 20) {
     case 128:
         return ASPEED_SDMC_AST2500_128MB;
     case 256:
@@ -177,8 +178,9 @@ static int ast2500_rambits(void)
     }
 
     /* use a common default */
-    error_report("warning: Invalid RAM size 0x" RAM_ADDR_FMT
-                 ". Using default 512M", ram_size);
+    error_report("warning: Invalid RAM size 0x%" PRIx64
+                 ". Using default 512M", s->ram_size);
+    s->ram_size = 512 << 20;
     return ASPEED_SDMC_AST2500_512MB;
 }
 
@@ -222,11 +224,11 @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
 
     switch (s->silicon_rev) {
     case AST2400_A0_SILICON_REV:
-        s->ram_bits = ast2400_rambits();
+        s->ram_bits = ast2400_rambits(s);
         break;
     case AST2500_A0_SILICON_REV:
     case AST2500_A1_SILICON_REV:
-        s->ram_bits = ast2500_rambits();
+        s->ram_bits = ast2500_rambits(s);
         break;
     default:
         g_assert_not_reached();
@@ -249,6 +251,7 @@ static const VMStateDescription vmstate_aspeed_sdmc = {
 
 static Property aspeed_sdmc_properties[] = {
     DEFINE_PROP_UINT32("silicon-rev", AspeedSDMCState, silicon_rev, 0),
+    DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0),
     DEFINE_PROP_END_OF_LIST(),
 };