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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-03-31 11:59:49 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-06-09 09:21:10 +0200 |
| commit | 1a5a5570889df9cdd42dd85223e03a5f35025a86 (patch) | |
| tree | 80a7d9272e756914fde5629014bf4e9596dd333a /hw/misc/grlib_ahb_apb_pnp.c | |
| parent | bb15013ef34617eb1344f5276292cadd326c21b2 (diff) | |
| download | focaccia-qemu-1a5a5570889df9cdd42dd85223e03a5f35025a86.tar.gz focaccia-qemu-1a5a5570889df9cdd42dd85223e03a5f35025a86.zip | |
hw/misc/grlib_ahb_apb_pnp: Fix AHB PnP 8-bit accesses
The Plug & Play region of the AHB/APB bridge can be accessed
by various word size, however the implementation is clearly
restricted to 32-bit:
static uint64_t grlib_ahb_pnp_read(void *opaque, hwaddr offset, unsigned size)
{
AHBPnp *ahb_pnp = GRLIB_AHB_PNP(opaque);
return ahb_pnp->regs[offset >> 2];
}
Similarly to commit 0fbe394a64 with the APB PnP registers,
set the MemoryRegionOps::impl min/max fields to 32-bit, so
memory.c::access_with_adjusted_size() can adjust when the
access is not 32-bit.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com>
Message-Id: <20200331105048.27989-4-f4bug@amsat.org>
Diffstat (limited to 'hw/misc/grlib_ahb_apb_pnp.c')
| -rw-r--r-- | hw/misc/grlib_ahb_apb_pnp.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/hw/misc/grlib_ahb_apb_pnp.c b/hw/misc/grlib_ahb_apb_pnp.c index 72a8764776..d22ed00206 100644 --- a/hw/misc/grlib_ahb_apb_pnp.c +++ b/hw/misc/grlib_ahb_apb_pnp.c @@ -146,6 +146,10 @@ static const MemoryRegionOps grlib_ahb_pnp_ops = { .read = grlib_ahb_pnp_read, .write = grlib_ahb_pnp_write, .endianness = DEVICE_BIG_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, }; static void grlib_ahb_pnp_realize(DeviceState *dev, Error **errp) |