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authorPeter Maydell <peter.maydell@linaro.org>2025-07-18 18:30:29 +0100
committerPeter Maydell <peter.maydell@linaro.org>2025-07-21 11:13:55 +0100
commit17f6436822ff600cae4590c4b06b3321c97f1f42 (patch)
tree7f312d6823cf0fae9843f25748bfe2acb77798f4 /hw/misc/ivshmem-pci.c
parent67fbc4c8079226eb9e47369cc45eb3fe56c3c9c3 (diff)
downloadfocaccia-qemu-17f6436822ff600cae4590c4b06b3321c97f1f42.tar.gz
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target/arm: Correct sense of FPCR.AH test for FMAXQV and FMINQV
When we implemented the FMAXQV and FMINQV insns we accidentally
inverted the sense of the FPCR.AH test, so we gave the AH=1 behaviour
when FPCR.AH was zero, and vice-versa.  (The difference is limited to
handling of negative zero and NaN inputs.)

Fixes: 1de7ecfc12d05 ("target/arm: Implement FADDQV, F{MIN, MAX}{NM}QV for SVE2p1")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250718173032.2498900-8-peter.maydell@linaro.org
Diffstat (limited to 'hw/misc/ivshmem-pci.c')
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