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authorPeter Maydell <peter.maydell@linaro.org>2020-06-25 21:20:44 +0100
committerPeter Maydell <peter.maydell@linaro.org>2020-06-25 21:20:45 +0100
commit5acc270a355120ce967ca1f1eeca0abbdb9303c8 (patch)
tree21be498ec58b49e33c3a2c88a59ba1b1053bc00a /hw/misc/macio/cuda.c
parent63d211993b73ca9ac2bc618afeb61a698e9f5198 (diff)
parent8a3a81478dcc592518069125a6ad271fe5511b95 (diff)
downloadfocaccia-qemu-5acc270a355120ce967ca1f1eeca0abbdb9303c8.tar.gz
focaccia-qemu-5acc270a355120ce967ca1f1eeca0abbdb9303c8.zip
Merge remote-tracking branch 'remotes/xtensa/tags/20200625-xtensa' into staging
target/xtensa fixes for 5.1:

- fix access to special registers missing in the core configuration;
- fix simcall opcode behavior for new hardware;
- drop gen_io_end call from xtensa translator.

# gpg: Signature made Thu 25 Jun 2020 09:08:58 BST
# gpg:                using RSA key 2B67854B98E5327DCDEB17D851F9CC91F83FA044
# gpg:                issuer "jcmvbkbc@gmail.com"
# gpg: Good signature from "Max Filippov <filippov@cadence.com>" [unknown]
# gpg:                 aka "Max Filippov <max.filippov@cogentembedded.com>" [full]
# gpg:                 aka "Max Filippov <jcmvbkbc@gmail.com>" [full]
# Primary key fingerprint: 2B67 854B 98E5 327D CDEB  17D8 51F9 CC91 F83F A044

* remotes/xtensa/tags/20200625-xtensa:
  target/xtensa: drop gen_io_end call
  target/xtensa: fix simcall for newer hardware
  target/xtensa: fetch HW version from configuration overlay
  target/xtensa: work around missing SR definitions

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/misc/macio/cuda.c')
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