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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-07-04 14:33:05 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-07-04 14:33:05 +0100 |
| commit | 3173a1fd549b7fa0f7029b2c6a6b86ba6efa92aa (patch) | |
| tree | 7ab44b3f4610cea6c687f0c127b83e09eb24f0ec /hw/misc/max111x.c | |
| parent | 9b9611c85d810f8f94a007b7ed7103a417fd25ba (diff) | |
| parent | e1ad9bc405afbd7581831ca1705f39e73c94c5ff (diff) | |
| download | focaccia-qemu-3173a1fd549b7fa0f7029b2c6a6b86ba6efa92aa.tar.gz focaccia-qemu-3173a1fd549b7fa0f7029b2c6a6b86ba6efa92aa.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20160704' into staging
target-arm queue: * fix semihosting SYS_HEAPINFO call for A64 guests * fix crash if guest tries to write to ROM on imx boards * armv7m_nvic: fix crash for debugger reads from some registers * virt: mark PCIe host controller as dma-coherent in the DT * add data-driven register API * Xilinx Zynq: add devcfg device model * m25p80: fix various bugs * ast2400: add SMC controllers and SPI flash slaves # gpg: Signature made Mon 04 Jul 2016 13:17:34 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20160704: (23 commits) ast2400: create SPI flash slaves ast2400: add SPI flash slaves ast2400: add SMC controllers (FMC and SPI) m25p80: qdev-ify drive property m25p80: change cur_addr to 32 bit integer m25p80: avoid out of bounds accesses m25p80: do not put iovec on the stack ssi: change ssi_slave_init to be a realize ops xilinx_zynq: Connect devcfg to the Zynq machine model dma: Add Xilinx Zynq devcfg device model register: Add block initialise helper register: QOMify register: Define REG and FIELD macros register: Add Memory API glue register: Add Register API bitops: Add MAKE_64BIT_MASK macro hw/arm/virt: mark the PCIe host controller as DMA coherent in the DT armv7m_nvic: Use qemu_get_cpu(0) instead of current_cpu memory: Assert that memory_region_init_rom_device() ops aren't NULL imx: Use memory_region_init_rom() for ROMs ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/misc/max111x.c')
| -rw-r--r-- | hw/misc/max111x.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c index 9014f0f705..2a277bdb86 100644 --- a/hw/misc/max111x.c +++ b/hw/misc/max111x.c @@ -147,14 +147,14 @@ static int max111x_init(SSISlave *d, int inputs) return 0; } -static int max1110_init(SSISlave *dev) +static void max1110_realize(SSISlave *dev, Error **errp) { - return max111x_init(dev, 8); + max111x_init(dev, 8); } -static int max1111_init(SSISlave *dev) +static void max1111_realize(SSISlave *dev, Error **errp) { - return max111x_init(dev, 4); + max111x_init(dev, 4); } void max111x_set_input(DeviceState *dev, int line, uint8_t value) @@ -183,7 +183,7 @@ static void max1110_class_init(ObjectClass *klass, void *data) { SSISlaveClass *k = SSI_SLAVE_CLASS(klass); - k->init = max1110_init; + k->realize = max1110_realize; } static const TypeInfo max1110_info = { @@ -196,7 +196,7 @@ static void max1111_class_init(ObjectClass *klass, void *data) { SSISlaveClass *k = SSI_SLAVE_CLASS(klass); - k->init = max1111_init; + k->realize = max1111_realize; } static const TypeInfo max1111_info = { |