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| author | Bin Meng <bin.meng@windriver.com> | 2020-10-28 13:30:02 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-11-03 07:17:23 -0800 |
| commit | 3400b15bbe0fbc672fee9a18268154b07a1fed2e (patch) | |
| tree | 8481d450f42487041164e70c0181c33983c0a1e7 /hw/misc/meson.build | |
| parent | 08b86e3b8f5209b1c39f22a6d367f347eaf0f8be (diff) | |
| download | focaccia-qemu-3400b15bbe0fbc672fee9a18268154b07a1fed2e.tar.gz focaccia-qemu-3400b15bbe0fbc672fee9a18268154b07a1fed2e.zip | |
hw/misc: Add Microchip PolarFire SoC DDR Memory Controller support
The PolarFire SoC DDR Memory Controller mainly includes 2 modules, called SGMII PHY module and the CFG module, as documented in the chipset datasheet. This creates a single file that groups these 2 modules, providing the minimum functionalities that make the HSS DDR initialization codes happy. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1603863010-15807-3-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/misc/meson.build')
| -rw-r--r-- | hw/misc/meson.build | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 4a06cbabef..2d7a517265 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -23,6 +23,7 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c')) softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c')) # RISC-V devices +softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_DMC', if_true: files('mchp_pfsoc_dmc.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c')) |