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| author | Marcin Nowakowski <marcin.nowakowski@fungible.com> | 2023-02-16 06:17:14 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2023-03-07 18:09:13 +0100 |
| commit | 9055ffd76edc80a6f0d134213522c8cbbafd0f36 (patch) | |
| tree | 40a31afcbc54c670ecfbd5dca6dd2cd76638061c /hw/misc/mips_cmgcr.c | |
| parent | a43972e1769b6b35c2c5826e707ea784242b6287 (diff) | |
| download | focaccia-qemu-9055ffd76edc80a6f0d134213522c8cbbafd0f36.tar.gz focaccia-qemu-9055ffd76edc80a6f0d134213522c8cbbafd0f36.zip | |
target/mips: Fix JALS32/J32 instruction handling for microMIPS
microMIPS J & JAL instructions perform a jump in a 128MB region and 5 top bits of the address need to be preserved. This is different behavior compared to standard mips systems, where the jump is executed within a 256MB region. Note that microMIPS32 instruction set documentation appears to have inconsistent information regarding JALX32 instruction - it is written in the doc that: "To execute a procedure call within the current 256 MB-aligned region (...) The low 26 bits of the target address is the target field shifted left 2 bits." But the target address is already 26 bits. Moreover, the operation description indicates that 28 bits are copied, so the statement about use of 26 bits is _most likely_ incorrect and the corresponding code remains the same as for standard mips instruction set. Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230216051717.3911212-2-marcin.nowakowski@fungible.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'hw/misc/mips_cmgcr.c')
0 files changed, 0 insertions, 0 deletions