diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2021-02-19 14:46:11 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-03-08 17:20:03 +0000 |
| commit | 39901aea063fb4be77a89d7badfed3998ad8fb4a (patch) | |
| tree | ea84f7ef9794300b0e1e2616e4fb421dc746a20d /hw/misc/mps2-scc.c | |
| parent | 7fa859914f58607bf874b9efecbe4be5726d91ac (diff) | |
| download | focaccia-qemu-39901aea063fb4be77a89d7badfed3998ad8fb4a.tar.gz focaccia-qemu-39901aea063fb4be77a89d7badfed3998ad8fb4a.zip | |
hw/misc/mps2-fpgaio: Support AN547 DBGCTRL register
For the AN547 image, the FPGAIO block has an extra DBGCTRL register, which is used to control the SPNIDEN, SPIDEN, NPIDEN and DBGEN inputs to the CPU. These signals control when the CPU permits use of the external debug interface. Our CPU models don't implement the external debug interface, so we model the register as reads-as-written. Implement the register, with a property defining whether it is present, and allow mps2-tz boards to specify that it is present. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210219144617.4782-39-peter.maydell@linaro.org
Diffstat (limited to 'hw/misc/mps2-scc.c')
0 files changed, 0 insertions, 0 deletions