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| author | Peter Maydell <peter.maydell@linaro.org> | 2018-08-14 17:17:21 +0100 |
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| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-08-14 17:17:21 +0100 |
| commit | 3d0e3080d8b7abcddc038d18e8401861c369c4c1 (patch) | |
| tree | 27b2dd726573b1e0ca10668c25b939e2753a662d /hw/misc/mst_fpga.c | |
| parent | ac656b166b57332ee397e9781810c956f4f5fde5 (diff) | |
| download | focaccia-qemu-3d0e3080d8b7abcddc038d18e8401861c369c4c1.tar.gz focaccia-qemu-3d0e3080d8b7abcddc038d18e8401861c369c4c1.zip | |
target/arm: Treat SCTLR_EL1.M as if it were zero when HCR_EL2.TGE is set
One of the required effects of setting HCR_EL2.TGE is that when SCR_EL3.NS is 1 then SCTLR_EL1.M must behave as if it is zero for all purposes except direct reads. That is, it effectively disables the MMU for the NS EL0/EL1 translation regime. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180724115950.17316-6-peter.maydell@linaro.org
Diffstat (limited to 'hw/misc/mst_fpga.c')
0 files changed, 0 insertions, 0 deletions