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authorPaolo Bonzini <pbonzini@redhat.com>2013-03-05 15:35:17 +0100
committerPaolo Bonzini <pbonzini@redhat.com>2014-05-13 13:21:51 +0200
commit4a92a558f49cb0693e36bd6d4f9217f298045be2 (patch)
tree931ba97c48f579e0c0abe0a45b23a0cecd816879 /hw/misc/mst_fpga.c
parent7b4d915e11ae7afb2d42a8cae90db26bc0c142b8 (diff)
downloadfocaccia-qemu-4a92a558f49cb0693e36bd6d4f9217f298045be2.tar.gz
focaccia-qemu-4a92a558f49cb0693e36bd6d4f9217f298045be2.zip
cpu: make CPU_INTERRUPT_RESET available on all targets
On the x86, some devices need access to the CPU reset pin (INIT#).
Provide a generic service to do this, using one of the internal
cpu_interrupt targets.  Generalize the PPC-specific code for
CPU_INTERRUPT_RESET to other targets.

Since PPC does not support migration across QEMU versions (its
machine types are not versioned yet), I picked the value that
is used on x86, CPU_INTERRUPT_TGT_INT_1.  Consequently, TGT_INT_2
and TGT_INT_3 are shifted down by one while keeping their value.

Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw/misc/mst_fpga.c')
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