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| author | Li Zhijian <lizhijian@fujitsu.com> | 2024-01-26 12:01:27 +0000 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2024-02-14 06:09:32 -0500 |
| commit | 729d45a6af06753d3e330f589c248fe9687c5cd5 (patch) | |
| tree | b2a37a1e9a2f7afb0692f29de70f6df9981e46d3 /hw/misc/mst_fpga.c | |
| parent | f7509f462c788a347521f90f19d623908c4fbcc5 (diff) | |
| download | focaccia-qemu-729d45a6af06753d3e330f589c248fe9687c5cd5.tar.gz focaccia-qemu-729d45a6af06753d3e330f589c248fe9687c5cd5.zip | |
hw/cxl: Pass CXLComponentState to cache_mem_ops
cache_mem_ops.{read,write}() interprets opaque as
CXLComponentState(cxl_cstate) instead of ComponentRegisters(cregs).
Fortunately, cregs is the first member of cxl_cstate, so their values are
the same.
Fixes: 9e58f52d3f8 ("hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5)")
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Signed-off-by: Li Zhijian <lizhijian@fujitsu.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20240126120132.24248-8-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/misc/mst_fpga.c')
0 files changed, 0 insertions, 0 deletions