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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-03-23 12:43:39 -0600 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2021-05-04 11:41:25 +1000 |
| commit | 75da499733696889453b3fda9ae0f0f5c28fcd6b (patch) | |
| tree | 52d79d1212ab217d85909f61af076957004b00f0 /hw/misc/mst_fpga.c | |
| parent | d764184ddb22a7a41a293e54c26cfe1717167a3f (diff) | |
| download | focaccia-qemu-75da499733696889453b3fda9ae0f0f5c28fcd6b.tar.gz focaccia-qemu-75da499733696889453b3fda9ae0f0f5c28fcd6b.zip | |
linux-user/ppc: Fix msr updates for signal handling
In save_user_regs, there are two bugs where we OR in a bit number instead of the bit, clobbering the low bits of MSR. However: The MSR_VR and MSR_SPE bits control the availability of the insns. If the bits were not already set in MSR, then any attempt to access those registers would result in SIGILL. For linux-user, we always initialize MSR to the capabilities of the cpu. We *could* add checks vs MSR where we currently check insn_flags and insn_flags2, but we know they match. Also, there's a stray cut-and-paste comment in restore. Then, do not force little-endian binaries into big-endian mode. Finally, use ppc_store_msr for the update to affect hflags. Which is the reason none of these bugs were previously noticed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210323184340.619757-10-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/misc/mst_fpga.c')
0 files changed, 0 insertions, 0 deletions