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| author | Bin Meng <bin.meng@windriver.com> | 2020-09-01 09:39:09 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-09-09 15:54:19 -0700 |
| commit | ce908a2f6f6d6e1d8ede485ee3f9f7d36ee3533c (patch) | |
| tree | 2a39318b0b288230d37d6fd82561f96272e33d06 /hw/misc/sifive_u_prci.c | |
| parent | 47374b0761c1e3b6bff210dbb9d1a965e71c213e (diff) | |
| download | focaccia-qemu-ce908a2f6f6d6e1d8ede485ee3f9f7d36ee3533c.tar.gz focaccia-qemu-ce908a2f6f6d6e1d8ede485ee3f9f7d36ee3533c.zip | |
hw/riscv: microchip_pfsoc: Hook GPIO controllers
Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems enough to create unimplemented devices to cover their register spaces at this point. With this commit, QEMU can boot to U-Boot (2nd stage bootloader) all the way to the Linux shell login prompt, with a modified HSS (1st stage bootloader). For detailed instructions on how to create images for the Icicle Kit board, please check QEMU RISC-V WiKi page at: https://wiki.qemu.org/Documentation/Platforms/RISCV Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <1598924352-89526-15-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/misc/sifive_u_prci.c')
0 files changed, 0 insertions, 0 deletions