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| author | Taylor Simpson <ltaylorsimpson@gmail.com> | 2024-06-13 12:22:09 -0600 |
|---|---|---|
| committer | Brian Cain <bcain@quicinc.com> | 2024-08-07 20:34:41 -0700 |
| commit | 523e45ac5b881237bd03934751d44767e5716620 (patch) | |
| tree | 4a2fd23e6544509a2f58d520df19ab50ccd8c1d9 /hw/misc/stm32l4x5_rcc.c | |
| parent | 6146060a6891848f854b0ed1e46e020a6fdc77c2 (diff) | |
| download | focaccia-qemu-523e45ac5b881237bd03934751d44767e5716620.tar.gz focaccia-qemu-523e45ac5b881237bd03934751d44767e5716620.zip | |
Hexagon: lldb read/write predicate registers p0/p1/p2/p3
hexagon-core.xml only exposes register p3_0 which is an alias that
aggregates the predicate registers. It is more convenient for users
to interact directly with the predicate registers.
Tested with lldb downloaded from this location
https://github.com/llvm/llvm-project/releases/download/llvmorg-18.1.4/clang+llvm-18.1.4-x86_64-linux-gnu-ubuntu-18.04.tar.xz
BEFORE:
(lldb) reg read p3_0
p3_0 = 0x00000000
(lldb) reg read p0
error: Invalid register name 'p0'.
(lldb) reg write p1 0xf
error: Register not found for 'p1'.
AFTER:
(lldb) reg read p3_0
p3_0 = 0x00000000
(lldb) reg read p0
p0 = 0x00
(lldb) reg read -s 1
Predicate Registers:
p0 = 0x00
p1 = 0x00
p2 = 0x00
p3 = 0x00
(lldb) reg write p1 0xf
(lldb) reg read p3_0
p3_0 = 0x00000f00
(lldb) reg write p3_0 0xff00ff00
(lldb) reg read -s 1
Predicate Registers:
p0 = 0x00
p1 = 0xff
p2 = 0x00
p3 = 0xff
Signed-off-by: Taylor Simpson <ltaylorsimpson@gmail.com>
Reviewed-by: Brian Cain <bcain@quicinc.com>
Reviewed-by: Matheus Tavares Bernardino <quic_mathbern@quicinc.com>
Message-Id: <20240613182209.140082-1-ltaylorsimpson@gmail.com>
Signed-off-by: Brian Cain <bcain@quicinc.com>
Diffstat (limited to 'hw/misc/stm32l4x5_rcc.c')
0 files changed, 0 insertions, 0 deletions