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| author | qianfan Zhao <qianfanguijin@163.com> | 2023-06-06 10:19:33 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2023-06-06 10:19:33 +0100 |
| commit | 05def917e113ef95ef712ffd96d614203f5e8397 (patch) | |
| tree | db2fc8e96bec4f3e00895d242630d14f28e1db47 /hw/misc/trace-events | |
| parent | 0de1b69315b1b386d96282fa0b407f568fc5ede9 (diff) | |
| download | focaccia-qemu-05def917e113ef95ef712ffd96d614203f5e8397.tar.gz focaccia-qemu-05def917e113ef95ef712ffd96d614203f5e8397.zip | |
hw: arm: allwinner-sramc: Add SRAM Controller support for R40
Only a few important registers are added, especially the SRAM_VER register. Signed-off-by: qianfan Zhao <qianfanguijin@163.com> Reviewed-by: Niek Linnenbank <nieklinnenbank@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/misc/trace-events')
| -rw-r--r-- | hw/misc/trace-events | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 8b68f07765..4d1a0e17af 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -33,6 +33,10 @@ allwinner_r40_dramphy_write(uint64_t offset, uint64_t data, unsigned size) "writ allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32 +# allwinner-sramc.c +allwinner_sramc_read(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 +allwinner_sramc_write(uint64_t offset, uint64_t data) "offset 0x%" PRIx64 " data 0x%" PRIx64 + # avr_power.c avr_power_read(uint8_t value) "power_reduc read value:%u" avr_power_write(uint8_t value) "power_reduc write value:%u" |