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| author | Hao Wu <wuhaotsh@google.com> | 2025-02-19 10:46:00 -0800 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-02-20 15:22:21 +0000 |
| commit | ca2fd966ea90b2ca02a4eff1afc2b89e963680a1 (patch) | |
| tree | 31b295dab04ff68ddda3fdfdda8ca91b739197bc /hw/misc/trace-events | |
| parent | 0ad46bbb56585fc3900f803747c485529869ca22 (diff) | |
| download | focaccia-qemu-ca2fd966ea90b2ca02a4eff1afc2b89e963680a1.tar.gz focaccia-qemu-ca2fd966ea90b2ca02a4eff1afc2b89e963680a1.zip | |
hw/misc: Support 8-bytes memop in NPCM GCR module
The NPCM8xx GCR device can be accessed with 64-bit memory operations. This patch supports that. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Hao Wu <wuhaotsh@google.com> Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Message-id: 20250219184609.1839281-10-wuhaotsh@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/misc/trace-events')
| -rw-r--r-- | hw/misc/trace-events | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 0f7204a237..f25dbd6030 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -135,8 +135,8 @@ npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " valu npcm7xx_clk_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 # npcm_gcr.c -npcm_gcr_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 -npcm_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx32 +npcm_gcr_read(uint64_t offset, uint64_t value) " offset: 0x%04" PRIx64 " value: 0x%08" PRIx64 +npcm_gcr_write(uint64_t offset, uint64_t value) "offset: 0x%04" PRIx64 " value: 0x%08" PRIx64 # npcm7xx_mft.c npcm7xx_mft_read(const char *name, uint64_t offset, uint16_t value) "%s: offset: 0x%04" PRIx64 " value: 0x%04" PRIx16 |