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authorRomán Cárdenas Rodríguez <rcardenas.rod@gmail.com>2024-10-14 17:05:50 +0100
committerPeter Maydell <peter.maydell@linaro.org>2024-10-15 11:29:45 +0100
commitd1613f2a5395f52a6537b0117bb219d832213489 (patch)
tree37e992de159a4ab03763f5f34d2fa436af389db1 /hw/misc/trace-events
parenta5397d805d519f89f35bade33c197cf7e460c9c3 (diff)
downloadfocaccia-qemu-d1613f2a5395f52a6537b0117bb219d832213489.tar.gz
focaccia-qemu-d1613f2a5395f52a6537b0117bb219d832213489.zip
hw/misc/stm32_rcc: Implement RCC device for STM32F4 SoCs
Generic RCC class for STM32 devices.  It can be used for most of
the STM32 chips.  Note that it only implements enable and reset
capabilities.

Signed-off-by: Roman Cardenas Rodriguez <rcardenas.rod@gmail.com>
[PMM: tweaked commit message, added MAINTAINERS lines]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/misc/trace-events')
-rw-r--r--hw/misc/trace-events6
1 files changed, 6 insertions, 0 deletions
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 1be0717c0c..b9fbcb0924 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -156,6 +156,12 @@ npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0
 npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u"
 npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u"
 
+# stm32_rcc.c
+stm32_rcc_read(uint64_t addr, uint64_t data) "reg read: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
+stm32_rcc_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
+stm32_rcc_pulse_enable(int line, int level) "Enable: %d to %d"
+stm32_rcc_pulse_reset(int line, int level) "Reset: %d to %d"
+
 # stm32f4xx_syscfg.c
 stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interrupt: GPIO: %d, Line: %d; Level: %d"
 stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"