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| author | Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> | 2018-06-13 09:30:13 +0100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2018-06-16 16:32:33 +1000 |
| commit | 7f5d6517e303e39d79f57ca92919725e03c9fad8 (patch) | |
| tree | e8c6b481f87c7a94e3aff2333112b53f1ca4a1c5 /hw/misc | |
| parent | 52b438815ecc1cb799d943ef4fd710fe67cc7702 (diff) | |
| download | focaccia-qemu-7f5d6517e303e39d79f57ca92919725e03c9fad8.tar.gz focaccia-qemu-7f5d6517e303e39d79f57ca92919725e03c9fad8.zip | |
mos6522: only clear the shift register interrupt upon write
According to the 6522 datasheet the shift register (SR) interrupt flag is cleared upon write with no mention of any other interrupt flags. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/misc')
| -rw-r--r-- | hw/misc/mos6522.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index 44eb306cf1..ad5041d8c0 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -241,7 +241,7 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size) break; case VIA_REG_SR: val = s->sr; - s->ifr &= ~(SR_INT | CB1_INT | CB2_INT); + s->ifr &= ~SR_INT; mos6522_update_irq(s); break; case VIA_REG_ACR: |