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| author | Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> | 2020-05-12 20:24:52 +0530 |
|---|---|---|
| committer | Jason Wang <jasowang@redhat.com> | 2020-06-18 21:05:51 +0800 |
| commit | 15baf5e23743871820504be6afb1bae24d1211c2 (patch) | |
| tree | d4f98e57246d7c4e0df5c45e0fb2f76f84714f60 /hw/net/cadence_gem.c | |
| parent | d48cb519b35010a90f18df915d187e566bf10c3e (diff) | |
| download | focaccia-qemu-15baf5e23743871820504be6afb1bae24d1211c2.tar.gz focaccia-qemu-15baf5e23743871820504be6afb1bae24d1211c2.zip | |
net: cadence_gem: Update the reset value for interrupt mask register
Mask all interrupt on reset. Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
Diffstat (limited to 'hw/net/cadence_gem.c')
| -rw-r--r-- | hw/net/cadence_gem.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 2211550d2b..df6d8186ca 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1375,6 +1375,7 @@ static void gem_reset(DeviceState *d) s->regs[GEM_DESCONF2] = 0x2ab10000 | s->jumbo_max_len; s->regs[GEM_DESCONF5] = 0x002f2045; s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK; + s->regs[GEM_INT_Q1_MASK] = 0x00000CE6; s->regs[GEM_JUMBO_MAX_LEN] = s->jumbo_max_len; if (s->num_priority_queues > 1) { |