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| author | Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> | 2015-05-29 11:52:35 +0530 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2015-06-03 16:03:03 +0300 |
| commit | 2801339f2fb2534ccf01561d274398328bdd446d (patch) | |
| tree | 96962ba0a29c40330dd3687e4913524d835bb71e /hw/net/cadence_gem.c | |
| parent | 8b8f1c7e9ddb2e88a144638f6527bf70e32343e3 (diff) | |
| download | focaccia-qemu-2801339f2fb2534ccf01561d274398328bdd446d.tar.gz focaccia-qemu-2801339f2fb2534ccf01561d274398328bdd446d.zip | |
cadence_gem: Fix Rx buffer size field mask
This patch corrects the Rx buffer size field mask to mask bits 23 to 16 to match Xilinx UG585 documentation. Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Diffstat (limited to 'hw/net/cadence_gem.c')
| -rw-r--r-- | hw/net/cadence_gem.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index dafe91421b..494a346cf6 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -155,7 +155,7 @@ #define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */ #define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */ -#define GEM_DMACFG_RBUFSZ_M 0x007F0000 /* DMA RX Buffer Size mask */ +#define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */ #define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */ #define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */ #define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */ |