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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-04-17 21:37:26 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-04-17 21:37:26 +0100 |
| commit | 2d03b49c3f225994c4b0b46146437d8c887d6774 (patch) | |
| tree | 00663246afe656b777e3c218cfea25e7ed32ffc2 /hw/net/cadence_gem.c | |
| parent | c6138aabfb2a8769392d605dc1e339b3095aab6a (diff) | |
| parent | e44a90c59697cf98e05619fbb6f77a403d347495 (diff) | |
| download | focaccia-qemu-2d03b49c3f225994c4b0b46146437d8c887d6774.tar.gz focaccia-qemu-2d03b49c3f225994c4b0b46146437d8c887d6774.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140417-1' into staging
target-arm queue: * AArch64 system mode support; this is all the CPU emulation code but not the virt board support * cadence_ttc match register bugfix * Allwinner A10 PIC, PIT and ethernet fixes [with update to avoid duplicate typedef] * zynq-slcr rewrite * cadence_gem bugfix * fix for SMLALD/SMLSLD insn in A32 * fix for SQXTUN in A64 # gpg: Signature made Thu 17 Apr 2014 21:35:57 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" * remotes/pmaydell/tags/pull-target-arm-20140417-1: (51 commits) target-arm: A64: fix unallocated test of scalar SQXTUN arm: translate.c: Fix smlald Instruction net: cadence_gem: Make phy respond to broadcast misc: zynq_slcr: Make DB_PRINTs always compile misc: zynq_slcr: Convert SBD::init to object init misc: zynq-slcr: Rewrite allwinner-emac: update irq status after writes to interrupt registers allwinner-emac: set autonegotiation complete bit on link up allwinner-a10-pit: implement prescaler and source selection allwinner-a10-pit: use level triggered interrupts allwinner-a10-pit: avoid generation of spurious interrupts allwinner-a10-pic: fix behaviour of pending register allwinner-a10-pic: set vector address when an interrupt is pending timer: cadence_ttc: Fix match register write logic target-arm/gdbstub64.c: remove useless 'break' statement. target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32 target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc target-arm: Make Cortex-A15 CBAR read-only target-arm: Implement CBAR for Cortex-A57 target-arm: Implement Cortex-A57 implementation-defined system registers ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/net/cadence_gem.c')
| -rw-r--r-- | hw/net/cadence_gem.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 92dc2f21fa..e34b25e734 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1093,7 +1093,7 @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) uint32_t phy_addr, reg_num; phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; - if (phy_addr == BOARD_PHY_ADDRESS) { + if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; retval &= 0xFFFF0000; retval |= gem_phy_read(s, reg_num); @@ -1193,7 +1193,7 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val, uint32_t phy_addr, reg_num; phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; - if (phy_addr == BOARD_PHY_ADDRESS) { + if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) { reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; gem_phy_write(s, reg_num, val); } |