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| author | Bin Meng <bin.meng@windriver.com> | 2020-09-01 09:39:04 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-09-09 15:54:18 -0700 |
| commit | 97ba42230b28636e02ab0af77738bb247e051dd4 (patch) | |
| tree | 3729a707093e871611f7c005a9c000233dd0bf9a /hw/net/cadence_gem.c | |
| parent | 898dc008e8cd474c21f98a63f151265673aea305 (diff) | |
| download | focaccia-qemu-97ba42230b28636e02ab0af77738bb247e051dd4.tar.gz focaccia-qemu-97ba42230b28636e02ab0af77738bb247e051dd4.zip | |
hw/dma: Add SiFive platform DMA controller emulation
Microchip PolarFire SoC integrates a DMA engine that supports: * Independent concurrent DMA transfers using 4 DMA channels * Generation of interrupts on various conditions during execution which is actually an IP reused from the SiFive FU540 chip. This creates a model to support both polling and interrupt modes. Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-10-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/net/cadence_gem.c')
0 files changed, 0 insertions, 0 deletions