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| author | Akihiko Odaki <akihiko.odaki@daynix.com> | 2023-05-23 11:43:18 +0900 |
|---|---|---|
| committer | Jason Wang <jasowang@redhat.com> | 2023-05-23 15:20:15 +0800 |
| commit | fe619f2005b15b14f718c56a57152c5c1c06b4c8 (patch) | |
| tree | b70f22126f948edd5ad94ae07948ca2c65d85e2d /hw/net/e1000e_core.c | |
| parent | 882e54da90a7634d6ccd6d451e2f6950bd68fe04 (diff) | |
| download | focaccia-qemu-fe619f2005b15b14f718c56a57152c5c1c06b4c8.tar.gz focaccia-qemu-fe619f2005b15b14f718c56a57152c5c1c06b4c8.zip | |
igb: Clear EICR bits for delayed MSI-X interrupts
Section 7.3.4.1 says: > When auto-clear is enabled for an interrupt cause, the EICR bit is > set when a cause event mapped to this vector occurs. When the EITR > Counter reaches zero, the MSI-X message is sent on PCIe. Then the > EICR bit is cleared and enabled to be set by a new cause event Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
Diffstat (limited to 'hw/net/e1000e_core.c')
0 files changed, 0 insertions, 0 deletions