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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-01-12 21:23:25 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-01-12 21:23:25 +0000 |
| commit | f8e1d8852e393b3fd524fb005e38590063d99bc0 (patch) | |
| tree | cca172d99d56088dd2b6cc494e6051ddd21809f6 /hw/net/lan9118.c | |
| parent | b3f846c59d8405bb87c551187721fc92ff2f1b92 (diff) | |
| parent | 1ff5a063d60c7737de11465516331b8ca8700865 (diff) | |
| download | focaccia-qemu-f8e1d8852e393b3fd524fb005e38590063d99bc0.tar.gz focaccia-qemu-f8e1d8852e393b3fd524fb005e38590063d99bc0.zip | |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210112-1' into staging
target-arm queue: * arm: Support emulation of ARMv8.4-TTST extension * arm: Update cpu.h ID register field definitions * arm: Fix breakage of XScale instruction emulation * hw/net/lan9118: Fix RX Status FIFO PEEK value * npcm7xx: Add ADC and PWM emulation * ui/cocoa: Make "open docs" help menu entry work again when binary is run from the build tree * ui/cocoa: Fix openFile: deprecation on Big Sur * docs: Add qemu-storage-daemon(1) manpage to meson.build # gpg: Signature made Tue 12 Jan 2021 21:22:15 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210112-1: ui/cocoa: Fix openFile: deprecation on Big Sur hw/*: Use type casting for SysBusDevice in NPCM7XX hw/misc: Add QTest for NPCM7XX PWM Module hw/misc: Add a PWM module for NPCM7XX hw/adc: Add an ADC module for NPCM7XX hw/timer: Refactor NPCM7XX Timer to use CLK clock hw/misc: Add clock converter in NPCM7XX CLK module hw/net/lan9118: Add symbolic constants for register offsets hw/net/lan9118: Fix RX Status FIFO PEEK value target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns docs: Add qemu-storage-daemon(1) manpage to meson.build ui/cocoa: Update path to docs in build tree target/arm: add aarch32 ID register fields to cpu.h target/arm: add aarch64 ID register fields to cpu.h target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h target/arm: make ARMCPU.ctr 64-bit target/arm: make ARMCPU.clidr 64-bit target/arm: fix typo in cpu.h ID_AA64PFR1 field name target/arm: enable Small Translation tables in max CPU target/arm: ARMv8.4-TTST extension Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/net/lan9118.c')
| -rw-r--r-- | hw/net/lan9118.c | 26 |
1 files changed, 19 insertions, 7 deletions
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c index ab57c02c8e..abc796285a 100644 --- a/hw/net/lan9118.c +++ b/hw/net/lan9118.c @@ -40,6 +40,17 @@ do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0) do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0) #endif +/* The tx and rx fifo ports are a range of aliased 32-bit registers */ +#define RX_DATA_FIFO_PORT_FIRST 0x00 +#define RX_DATA_FIFO_PORT_LAST 0x1f +#define TX_DATA_FIFO_PORT_FIRST 0x20 +#define TX_DATA_FIFO_PORT_LAST 0x3f + +#define RX_STATUS_FIFO_PORT 0x40 +#define RX_STATUS_FIFO_PEEK 0x44 +#define TX_STATUS_FIFO_PORT 0x48 +#define TX_STATUS_FIFO_PEEK 0x4c + #define CSR_ID_REV 0x50 #define CSR_IRQ_CFG 0x54 #define CSR_INT_STS 0x58 @@ -1020,7 +1031,8 @@ static void lan9118_writel(void *opaque, hwaddr offset, offset &= 0xff; //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val); - if (offset >= 0x20 && offset < 0x40) { + if (offset >= TX_DATA_FIFO_PORT_FIRST && + offset <= TX_DATA_FIFO_PORT_LAST) { /* TX FIFO */ tx_fifo_push(s, val); return; @@ -1198,18 +1210,18 @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset, lan9118_state *s = (lan9118_state *)opaque; //DPRINTF("Read reg 0x%02x\n", (int)offset); - if (offset < 0x20) { + if (offset <= RX_DATA_FIFO_PORT_LAST) { /* RX FIFO */ return rx_fifo_pop(s); } switch (offset) { - case 0x40: + case RX_STATUS_FIFO_PORT: return rx_status_fifo_pop(s); - case 0x44: - return s->rx_status_fifo[s->tx_status_fifo_head]; - case 0x48: + case RX_STATUS_FIFO_PEEK: + return s->rx_status_fifo[s->rx_status_fifo_head]; + case TX_STATUS_FIFO_PORT: return tx_status_fifo_pop(s); - case 0x4c: + case TX_STATUS_FIFO_PEEK: return s->tx_status_fifo[s->tx_status_fifo_head]; case CSR_ID_REV: return 0x01180001; |