Merge tag 'pull-request-2022-11-11' of https://gitlab.com/thuth/qemu into staging

* Fix "unused variable" warnings from Clang 15
* Allow building of guest-agent without emulators or tools
* White space clean-ups
* Fixes for typos in the documentation

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# gpg: Signature made Fri 11 Nov 2022 05:27:34 EST
# gpg:                using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg:                issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg:                 aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg:                 aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg:                 aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3  EAB9 2ED9 D774 FE70 2DB5

* tag 'pull-request-2022-11-11' of https://gitlab.com/thuth/qemu:
  Fix several typos in documentation (found by codespell)
  net: Replace TAB indentations with spaces
  qga: Allow building of the guest agent without system emulators or tools
  libdecnumber/dpd/decimal64: Fix compiler warning from Clang 15
  host-libusb: Remove unused variable
  qemu-img: remove unused variable
  tulip: Remove unused variable
  rtl8139: Remove unused variable

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>

1 files changed, 69 insertions, 69 deletions

diff --git a/hw/net/ne2000.c b/hw/net/ne2000.c
index 6c17ee1ae2..3f31d04efb 100644
--- a/hw/net/ne2000.c
+++ b/hw/net/ne2000.c
@@ -36,89 +36,89 @@
 
 #define MAX_ETH_FRAME_SIZE 1514
 
-#define E8390_CMD	0x00  /* The command register (for all pages) */
+#define E8390_CMD       0x00    /* The command register (for all pages) */
 /* Page 0 register offsets. */
-#define EN0_CLDALO	0x01	/* Low byte of current local dma addr  RD */
-#define EN0_STARTPG	0x01	/* Starting page of ring bfr WR */
-#define EN0_CLDAHI	0x02	/* High byte of current local dma addr  RD */
-#define EN0_STOPPG	0x02	/* Ending page +1 of ring bfr WR */
-#define EN0_BOUNDARY	0x03	/* Boundary page of ring bfr RD WR */
-#define EN0_TSR		0x04	/* Transmit status reg RD */
-#define EN0_TPSR	0x04	/* Transmit starting page WR */
-#define EN0_NCR		0x05	/* Number of collision reg RD */
-#define EN0_TCNTLO	0x05	/* Low  byte of tx byte count WR */
-#define EN0_FIFO	0x06	/* FIFO RD */
-#define EN0_TCNTHI	0x06	/* High byte of tx byte count WR */
-#define EN0_ISR		0x07	/* Interrupt status reg RD WR */
-#define EN0_CRDALO	0x08	/* low byte of current remote dma address RD */
-#define EN0_RSARLO	0x08	/* Remote start address reg 0 */
-#define EN0_CRDAHI	0x09	/* high byte, current remote dma address RD */
-#define EN0_RSARHI	0x09	/* Remote start address reg 1 */
-#define EN0_RCNTLO	0x0a	/* Remote byte count reg WR */
-#define EN0_RTL8029ID0	0x0a	/* Realtek ID byte #1 RD */
-#define EN0_RCNTHI	0x0b	/* Remote byte count reg WR */
-#define EN0_RTL8029ID1	0x0b	/* Realtek ID byte #2 RD */
-#define EN0_RSR		0x0c	/* rx status reg RD */
-#define EN0_RXCR	0x0c	/* RX configuration reg WR */
-#define EN0_TXCR	0x0d	/* TX configuration reg WR */
-#define EN0_COUNTER0	0x0d	/* Rcv alignment error counter RD */
-#define EN0_DCFG	0x0e	/* Data configuration reg WR */
-#define EN0_COUNTER1	0x0e	/* Rcv CRC error counter RD */
-#define EN0_IMR		0x0f	/* Interrupt mask reg WR */
-#define EN0_COUNTER2	0x0f	/* Rcv missed frame error counter RD */
+#define EN0_CLDALO      0x01    /* Low byte of current local dma addr  RD */
+#define EN0_STARTPG     0x01    /* Starting page of ring bfr WR */
+#define EN0_CLDAHI      0x02    /* High byte of current local dma addr  RD */
+#define EN0_STOPPG      0x02    /* Ending page +1 of ring bfr WR */
+#define EN0_BOUNDARY    0x03    /* Boundary page of ring bfr RD WR */
+#define EN0_TSR         0x04    /* Transmit status reg RD */
+#define EN0_TPSR        0x04    /* Transmit starting page WR */
+#define EN0_NCR         0x05    /* Number of collision reg RD */
+#define EN0_TCNTLO      0x05    /* Low  byte of tx byte count WR */
+#define EN0_FIFO        0x06    /* FIFO RD */
+#define EN0_TCNTHI      0x06    /* High byte of tx byte count WR */
+#define EN0_ISR         0x07    /* Interrupt status reg RD WR */
+#define EN0_CRDALO      0x08    /* low byte of current remote dma address RD */
+#define EN0_RSARLO      0x08    /* Remote start address reg 0 */
+#define EN0_CRDAHI      0x09    /* high byte, current remote dma address RD */
+#define EN0_RSARHI      0x09    /* Remote start address reg 1 */
+#define EN0_RCNTLO      0x0a    /* Remote byte count reg WR */
+#define EN0_RTL8029ID0  0x0a    /* Realtek ID byte #1 RD */
+#define EN0_RCNTHI      0x0b    /* Remote byte count reg WR */
+#define EN0_RTL8029ID1  0x0b    /* Realtek ID byte #2 RD */
+#define EN0_RSR         0x0c    /* rx status reg RD */
+#define EN0_RXCR        0x0c    /* RX configuration reg WR */
+#define EN0_TXCR        0x0d    /* TX configuration reg WR */
+#define EN0_COUNTER0    0x0d    /* Rcv alignment error counter RD */
+#define EN0_DCFG        0x0e    /* Data configuration reg WR */
+#define EN0_COUNTER1    0x0e    /* Rcv CRC error counter RD */
+#define EN0_IMR         0x0f    /* Interrupt mask reg WR */
+#define EN0_COUNTER2    0x0f    /* Rcv missed frame error counter RD */
 
 #define EN1_PHYS        0x11
 #define EN1_CURPAG      0x17
 #define EN1_MULT        0x18
 
-#define EN2_STARTPG	0x21	/* Starting page of ring bfr RD */
-#define EN2_STOPPG	0x22	/* Ending page +1 of ring bfr RD */
+#define EN2_STARTPG     0x21    /* Starting page of ring bfr RD */
+#define EN2_STOPPG      0x22    /* Ending page +1 of ring bfr RD */
 
-#define EN3_CONFIG0	0x33
-#define EN3_CONFIG1	0x34
-#define EN3_CONFIG2	0x35
-#define EN3_CONFIG3	0x36
+#define EN3_CONFIG0     0x33
+#define EN3_CONFIG1     0x34
+#define EN3_CONFIG2     0x35
+#define EN3_CONFIG3     0x36
 
 /*  Register accessed at EN_CMD, the 8390 base addr.  */
-#define E8390_STOP	0x01	/* Stop and reset the chip */
-#define E8390_START	0x02	/* Start the chip, clear reset */
-#define E8390_TRANS	0x04	/* Transmit a frame */
-#define E8390_RREAD	0x08	/* Remote read */
-#define E8390_RWRITE	0x10	/* Remote write  */
-#define E8390_NODMA	0x20	/* Remote DMA */
-#define E8390_PAGE0	0x00	/* Select page chip registers */
-#define E8390_PAGE1	0x40	/* using the two high-order bits */
-#define E8390_PAGE2	0x80	/* Page 3 is invalid. */
+#define E8390_STOP      0x01    /* Stop and reset the chip */
+#define E8390_START     0x02    /* Start the chip, clear reset */
+#define E8390_TRANS     0x04    /* Transmit a frame */
+#define E8390_RREAD     0x08    /* Remote read */
+#define E8390_RWRITE    0x10    /* Remote write  */
+#define E8390_NODMA     0x20    /* Remote DMA */
+#define E8390_PAGE0     0x00    /* Select page chip registers */
+#define E8390_PAGE1     0x40    /* using the two high-order bits */
+#define E8390_PAGE2     0x80    /* Page 3 is invalid. */
 
 /* Bits in EN0_ISR - Interrupt status register */
-#define ENISR_RX	0x01	/* Receiver, no error */
-#define ENISR_TX	0x02	/* Transmitter, no error */
-#define ENISR_RX_ERR	0x04	/* Receiver, with error */
-#define ENISR_TX_ERR	0x08	/* Transmitter, with error */
-#define ENISR_OVER	0x10	/* Receiver overwrote the ring */
-#define ENISR_COUNTERS	0x20	/* Counters need emptying */
-#define ENISR_RDC	0x40	/* remote dma complete */
-#define ENISR_RESET	0x80	/* Reset completed */
-#define ENISR_ALL	0x3f	/* Interrupts we will enable */
+#define ENISR_RX        0x01    /* Receiver, no error */
+#define ENISR_TX        0x02    /* Transmitter, no error */
+#define ENISR_RX_ERR    0x04    /* Receiver, with error */
+#define ENISR_TX_ERR    0x08    /* Transmitter, with error */
+#define ENISR_OVER      0x10    /* Receiver overwrote the ring */
+#define ENISR_COUNTERS  0x20    /* Counters need emptying */
+#define ENISR_RDC       0x40    /* remote dma complete */
+#define ENISR_RESET     0x80    /* Reset completed */
+#define ENISR_ALL       0x3f    /* Interrupts we will enable */
 
 /* Bits in received packet status byte and EN0_RSR*/
-#define ENRSR_RXOK	0x01	/* Received a good packet */
-#define ENRSR_CRC	0x02	/* CRC error */
-#define ENRSR_FAE	0x04	/* frame alignment error */
-#define ENRSR_FO	0x08	/* FIFO overrun */
-#define ENRSR_MPA	0x10	/* missed pkt */
-#define ENRSR_PHY	0x20	/* physical/multicast address */
-#define ENRSR_DIS	0x40	/* receiver disable. set in monitor mode */
-#define ENRSR_DEF	0x80	/* deferring */
+#define ENRSR_RXOK      0x01    /* Received a good packet */
+#define ENRSR_CRC       0x02    /* CRC error */
+#define ENRSR_FAE       0x04    /* frame alignment error */
+#define ENRSR_FO        0x08    /* FIFO overrun */
+#define ENRSR_MPA       0x10    /* missed pkt */
+#define ENRSR_PHY       0x20    /* physical/multicast address */
+#define ENRSR_DIS       0x40    /* receiver disable. set in monitor mode */
+#define ENRSR_DEF       0x80    /* deferring */
 
 /* Transmitted packet status, EN0_TSR. */
-#define ENTSR_PTX 0x01	/* Packet transmitted without error */
-#define ENTSR_ND  0x02	/* The transmit wasn't deferred. */
-#define ENTSR_COL 0x04	/* The transmit collided at least once. */
+#define ENTSR_PTX 0x01  /* Packet transmitted without error */
+#define ENTSR_ND  0x02  /* The transmit wasn't deferred. */
+#define ENTSR_COL 0x04  /* The transmit collided at least once. */
 #define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
-#define ENTSR_CRS 0x10	/* The carrier sense was lost. */
+#define ENTSR_CRS 0x10  /* The carrier sense was lost. */
 #define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
-#define ENTSR_CDH 0x40	/* The collision detect "heartbeat" signal was lost. */
+#define ENTSR_CDH 0x40  /* The collision detect "heartbeat" signal was lost. */
 #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
 
 void ne2000_reset(NE2000State *s)
@@ -425,13 +425,13 @@ static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
             ret = 0x43;
             break;
         case EN3_CONFIG0:
-            ret = 0;		/* 10baseT media */
+            ret = 0;          /* 10baseT media */
             break;
         case EN3_CONFIG2:
-            ret = 0x40;		/* 10baseT active */
+            ret = 0x40;       /* 10baseT active */
             break;
         case EN3_CONFIG3:
-            ret = 0x40;		/* Full duplex */
+            ret = 0x40;       /* Full duplex */
             break;
         default:
             ret = 0x00;