diff options
| author | Klaus Jensen <k.jensen@samsung.com> | 2024-12-16 13:53:06 +0100 |
|---|---|---|
| committer | Klaus Jensen <k.jensen@samsung.com> | 2025-02-25 12:55:21 +0100 |
| commit | d96a32de3fd0880a9340590fd279288e42e983c1 (patch) | |
| tree | 3f1cc0d12b832ecc45af2ba597a8629bb19ab3ef /hw/nvme/ctrl.c | |
| parent | b202fb549dc487c5611564e5d03286748586aa34 (diff) | |
| download | focaccia-qemu-d96a32de3fd0880a9340590fd279288e42e983c1.tar.gz focaccia-qemu-d96a32de3fd0880a9340590fd279288e42e983c1.zip | |
hw/nvme: be compliant wrt. dsm processing limits
The specification states that, > The controller shall set all three processing limit fields (i.e., the > DMRL, DMRSL and DMSL fields) to non-zero values or shall clear all > three processing limit fields to 0h. So, set the DMRL and DMSL fields in addition to DMRSL. Reviewed-by: Jesper Wendel Devantier <foss@defmacro.it> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Diffstat (limited to 'hw/nvme/ctrl.c')
| -rw-r--r-- | hw/nvme/ctrl.c | 24 |
1 files changed, 15 insertions, 9 deletions
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 2b73f60160..86e1c48fab 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -5639,7 +5639,9 @@ static uint16_t nvme_identify_ctrl_csi(NvmeCtrl *n, NvmeRequest *req) switch (c->csi) { case NVME_CSI_NVM: id_nvm->vsl = n->params.vsl; + id_nvm->dmrl = NVME_ID_CTRL_NVM_DMRL_MAX; id_nvm->dmrsl = cpu_to_le32(n->dmrsl); + id_nvm->dmsl = NVME_ID_CTRL_NVM_DMRL_MAX * n->dmrsl; break; case NVME_CSI_ZONED: @@ -6696,18 +6698,23 @@ static uint16_t nvme_aer(NvmeCtrl *n, NvmeRequest *req) return NVME_NO_COMPLETE; } -static void nvme_update_dmrsl(NvmeCtrl *n) +static void nvme_update_dsm_limits(NvmeCtrl *n, NvmeNamespace *ns) { - int nsid; + if (ns) { + n->dmrsl = + MIN_NON_ZERO(n->dmrsl, BDRV_REQUEST_MAX_BYTES / nvme_l2b(ns, 1)); - for (nsid = 1; nsid <= NVME_MAX_NAMESPACES; nsid++) { - NvmeNamespace *ns = nvme_ns(n, nsid); + return; + } + + for (uint32_t nsid = 1; nsid <= NVME_MAX_NAMESPACES; nsid++) { + ns = nvme_ns(n, nsid); if (!ns) { continue; } - n->dmrsl = MIN_NON_ZERO(n->dmrsl, - BDRV_REQUEST_MAX_BYTES / nvme_l2b(ns, 1)); + n->dmrsl = + MIN_NON_ZERO(n->dmrsl, BDRV_REQUEST_MAX_BYTES / nvme_l2b(ns, 1)); } } @@ -6795,7 +6802,7 @@ static uint16_t nvme_ns_attachment(NvmeCtrl *n, NvmeRequest *req) ctrl->namespaces[nsid] = NULL; ns->attached--; - nvme_update_dmrsl(ctrl); + nvme_update_dsm_limits(ctrl, NULL); break; @@ -8902,8 +8909,7 @@ void nvme_attach_ns(NvmeCtrl *n, NvmeNamespace *ns) n->namespaces[nsid] = ns; ns->attached++; - n->dmrsl = MIN_NON_ZERO(n->dmrsl, - BDRV_REQUEST_MAX_BYTES / nvme_l2b(ns, 1)); + nvme_update_dsm_limits(n, ns); } static void nvme_realize(PCIDevice *pci_dev, Error **errp) |