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| author | Lukasz Maniak <lukasz.maniak@linux.intel.com> | 2022-05-09 16:16:11 +0200 |
|---|---|---|
| committer | Klaus Jensen <k.jensen@samsung.com> | 2022-06-23 23:24:28 +0200 |
| commit | 99f48ae7aea70fb080f04bf1cc846cd6450bd11a (patch) | |
| tree | eeec8913da9527008b6b192cf8412765e43d1519 /hw/nvme/trace-events | |
| parent | 5e6f963f018f2ebb16c0f9586f17811163d62b4a (diff) | |
| download | focaccia-qemu-99f48ae7aea70fb080f04bf1cc846cd6450bd11a.tar.gz focaccia-qemu-99f48ae7aea70fb080f04bf1cc846cd6450bd11a.zip | |
hw/nvme: Add support for Secondary Controller List
Introduce handling for Secondary Controller List (Identify command with CNS value of 15h). Secondary controller ids are unique in the subsystem, hence they are reserved by it upon initialization of the primary controller to the number of sriov_max_vfs. ID reservation requires the addition of an intermediate controller slot state, so the reserved controller has the address 0xFFFF. A secondary controller is in the reserved state when it has no virtual function assigned, but its primary controller is realized. Secondary controller reservations are released to NULL when its primary controller is unregistered. Signed-off-by: Lukasz Maniak <lukasz.maniak@linux.intel.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Diffstat (limited to 'hw/nvme/trace-events')
| -rw-r--r-- | hw/nvme/trace-events | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/nvme/trace-events b/hw/nvme/trace-events index 1834b17cf2..889bbb3101 100644 --- a/hw/nvme/trace-events +++ b/hw/nvme/trace-events @@ -57,6 +57,7 @@ pci_nvme_identify_ctrl_csi(uint8_t csi) "identify controller, csi=0x%"PRIx8"" pci_nvme_identify_ns(uint32_t ns) "nsid %"PRIu32"" pci_nvme_identify_ctrl_list(uint8_t cns, uint16_t cntid) "cns 0x%"PRIx8" cntid %"PRIu16"" pci_nvme_identify_pri_ctrl_cap(uint16_t cntlid) "identify primary controller capabilities cntlid=%"PRIu16"" +pci_nvme_identify_sec_ctrl_list(uint16_t cntlid, uint8_t numcntl) "identify secondary controller list cntlid=%"PRIu16" numcntl=%"PRIu8"" pci_nvme_identify_ns_csi(uint32_t ns, uint8_t csi) "nsid=%"PRIu32", csi=0x%"PRIx8"" pci_nvme_identify_nslist(uint32_t ns) "nsid %"PRIu32"" pci_nvme_identify_nslist_csi(uint16_t ns, uint8_t csi) "nsid=%"PRIu16", csi=0x%"PRIx8"" |