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| author | Anthony Liguori <aliguori@us.ibm.com> | 2013-03-14 14:50:58 -0500 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2013-03-14 14:50:58 -0500 |
| commit | 3d34a4110c58bba120bc3d7c96c4b9571994c2a8 (patch) | |
| tree | 7bbd137a5886c67352f77ee11a94009ad4af52cd /hw/openrisc | |
| parent | 0ec4a8e63ce5244cdb2aa8ef93427898e3f6631b (diff) | |
| parent | 0ad6773f1151c9e172b0b714aada78655dda4cf4 (diff) | |
| download | focaccia-qemu-3d34a4110c58bba120bc3d7c96c4b9571994c2a8.tar.gz focaccia-qemu-3d34a4110c58bba120bc3d7c96c4b9571994c2a8.zip | |
Merge remote-tracking branch 'afaerber/qom-cpu' into staging
# By Andreas Färber (16) and Igor Mammedov (1) # Via Andreas Färber * afaerber/qom-cpu: target-lm32: Update VMStateDescription to LM32CPU target-arm: Override do_interrupt for ARMv7-M profile cpu: Replace do_interrupt() by CPUClass::do_interrupt method cpu: Pass CPUState to cpu_interrupt() exec: Pass CPUState to cpu_reset_interrupt() cpu: Move halted and interrupt_request fields to CPUState target-cris/helper.c: Update Coding Style target-i386: Update VMStateDescription to X86CPU cpu: Introduce cpu_class_set_vmsd() cpu: Register VMStateDescription through CPUState stubs: Add a vmstate_dummy struct for CONFIG_USER_ONLY vmstate: Make vmstate_register() static inline target-sh4: Move PVR/PRR/CVR into SuperHCPUClass target-sh4: Introduce SuperHCPU subclasses cpus: Replace open-coded CPU loop in qmp_memsave() with qemu_get_cpu() monitor: Use qemu_get_cpu() in monitor_set_cpu() cpu: Fix qemu_get_cpu() to return NULL if CPU not found
Diffstat (limited to 'hw/openrisc')
| -rw-r--r-- | hw/openrisc/cputimer.c | 4 | ||||
| -rw-r--r-- | hw/openrisc/pic_cpu.c | 5 |
2 files changed, 6 insertions, 3 deletions
diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c index f6c877f425..4144b34be7 100644 --- a/hw/openrisc/cputimer.c +++ b/hw/openrisc/cputimer.c @@ -73,8 +73,10 @@ static void openrisc_timer_cb(void *opaque) if ((cpu->env.ttmr & TTMR_IE) && qemu_timer_expired(cpu->env.timer, qemu_get_clock_ns(vm_clock))) { + CPUState *cs = CPU(cpu); + cpu->env.ttmr |= TTMR_IP; - cpu->env.interrupt_request |= CPU_INTERRUPT_TIMER; + cs->interrupt_request |= CPU_INTERRUPT_TIMER; } switch (cpu->env.ttmr & TTMR_M) { diff --git a/hw/openrisc/pic_cpu.c b/hw/openrisc/pic_cpu.c index 931511ec0f..ca0b7c11bd 100644 --- a/hw/openrisc/pic_cpu.c +++ b/hw/openrisc/pic_cpu.c @@ -25,6 +25,7 @@ static void openrisc_pic_cpu_handler(void *opaque, int irq, int level) { OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; + CPUState *cs = CPU(cpu); int i; uint32_t irq_bit = 1 << irq; @@ -40,9 +41,9 @@ static void openrisc_pic_cpu_handler(void *opaque, int irq, int level) for (i = 0; i < 32; i++) { if ((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i))) { - cpu_interrupt(&cpu->env, CPU_INTERRUPT_HARD); + cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { - cpu_reset_interrupt(&cpu->env, CPU_INTERRUPT_HARD); + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); cpu->env.picsr &= ~(1 << i); } } |