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| author | Jia Liu <proljc@gmail.com> | 2013-08-21 09:23:10 +0800 |
|---|---|---|
| committer | Jia Liu <proljc@gmail.com> | 2013-08-21 09:23:10 +0800 |
| commit | ed396e2b2d256c1628de7c11841b509455a76c03 (patch) | |
| tree | 02910fd93a6b2ceb9d688a70375578c9bf7ae9eb /hw/openrisc | |
| parent | b6d9766ddf5453e79e0c66c9348728ba44ba115f (diff) | |
| download | focaccia-qemu-ed396e2b2d256c1628de7c11841b509455a76c03.tar.gz focaccia-qemu-ed396e2b2d256c1628de7c11841b509455a76c03.zip | |
hw/openrisc: Fix masking in openrisc_pic_cpu_handler()
Consider the masking of PICSR and PICMR:
((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i)))
To correctly mask bits, we should use the bitwise AND "&" rather than
the logical AND "&&". Also, the loop is not necessary for masking.
Simply use (cpu->env.picsr & cpu->env.picmr).
Signed-off-by: Xi Wang <xi.wang@gmail.com>
Acked-by: Jia Liu <proljc@gmail.com>
Diffstat (limited to 'hw/openrisc')
| -rw-r--r-- | hw/openrisc/pic_cpu.c | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/hw/openrisc/pic_cpu.c b/hw/openrisc/pic_cpu.c index ca0b7c11bd..3fcee02619 100644 --- a/hw/openrisc/pic_cpu.c +++ b/hw/openrisc/pic_cpu.c @@ -26,7 +26,6 @@ static void openrisc_pic_cpu_handler(void *opaque, int irq, int level) { OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; CPUState *cs = CPU(cpu); - int i; uint32_t irq_bit = 1 << irq; if (irq > 31 || irq < 0) { @@ -39,13 +38,11 @@ static void openrisc_pic_cpu_handler(void *opaque, int irq, int level) cpu->env.picsr &= ~irq_bit; } - for (i = 0; i < 32; i++) { - if ((cpu->env.picsr && (1 << i)) && (cpu->env.picmr && (1 << i))) { - cpu_interrupt(cs, CPU_INTERRUPT_HARD); - } else { - cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); - cpu->env.picsr &= ~(1 << i); - } + if (cpu->env.picsr & cpu->env.picmr) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + cpu->env.picsr = 0; } } |