Introduce reset notifier order

Add the parameter 'order' to qemu_register_reset and sort callbacks on
registration. On system reset, callbacks with lower order will be
invoked before those with higher order. Update all existing users to the
standard order 0.

Note: At least for x86, the existing users seem to assume that handlers
are called in their registration order. Therefore, the patch preserves
this property. If someone feels bored, (s)he could try to identify this
dependency and express it properly on callback registration.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/hw/parallel.c b/hw/parallel.c
index dd2eedab79..f66e5eb7e3 100644
--- a/hw/parallel.c
+++ b/hw/parallel.c
@@ -448,7 +448,7 @@ ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr)
     s->irq = irq;
     s->chr = chr;
     parallel_reset(s);
-    qemu_register_reset(parallel_reset, s);
+    qemu_register_reset(parallel_reset, 0, s);
 
     if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) {
         s->hw_driver = 1;
@@ -541,7 +541,7 @@ ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq
     s->chr = chr;
     s->it_shift = it_shift;
     parallel_reset(s);
-    qemu_register_reset(parallel_reset, s);
+    qemu_register_reset(parallel_reset, 0, s);
 
     io_sw = cpu_register_io_memory(0, parallel_mm_read_sw, parallel_mm_write_sw, s);
     cpu_register_physical_memory(base, 8 << it_shift, io_sw);