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| author | Michael Tokarev <mjt@tls.msk.ru> | 2023-07-14 14:27:04 +0300 |
|---|---|---|
| committer | Michael Tokarev <mjt@tls.msk.ru> | 2023-09-20 07:54:34 +0300 |
| commit | f1c0cff8a28ac25f48ecaea672eb3d68250bb3c4 (patch) | |
| tree | db97cf9d628a18c15a28e0af6f92a818dbd80ef0 /hw/pci-host/designware.c | |
| parent | 2431f4f184339f679ff665c75e927fc24f7bd430 (diff) | |
| download | focaccia-qemu-f1c0cff8a28ac25f48ecaea672eb3d68250bb3c4.tar.gz focaccia-qemu-f1c0cff8a28ac25f48ecaea672eb3d68250bb3c4.zip | |
hw/pci: spelling fixes
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/pci-host/designware.c')
| -rw-r--r-- | hw/pci-host/designware.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 388d252ee2..6f5442f108 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -488,7 +488,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) /* * If no inbound iATU windows are configured, HW defaults to - * letting inbound TLPs to pass in. We emulate that by exlicitly + * letting inbound TLPs to pass in. We emulate that by explicitly * configuring first inbound window to cover all of target's * address space. * @@ -503,7 +503,7 @@ static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) &designware_pci_host_msi_ops, root, "pcie-msi", 0x4); /* - * We initially place MSI interrupt I/O region a adress 0 and + * We initially place MSI interrupt I/O region at address 0 and * disable it. It'll be later moved to correct offset and enabled * in designware_pcie_root_update_msi_mapping() as a part of * initialization done by guest OS |