Merge tag 'misc-fixes-20230330' of https://github.com/philmd/qemu into staging

- linux-user:
  . Don't use 16-bit UIDs with SPARC V9
  . Pick MIPS3 CPU by default to run NaN2008 ELF binaries

- HW:
  . Fix invalid GT64120 north bridge endianness register swap
  . Prevent NULL pointer dereference by SMBus devices

- Buildsys:
  . Fix compiling with liblzfse on Darwin

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmQli+8ACgkQ4+MsLN6t
# wN5GJw/8CqzhxQgp11u2ArQlz/zsXJd4d6goIAIefJK1H80FXhqblz3ZBICci0Mu
# vA9CCayQ72r2NYR71QNvK6WWAJRnWbwFYH5arbvFRlCtDKV/n/DSSqsytY0Pd9eZ
# YlGJQ8tjO2PNa+K6J1ElUDRDk+xPnWlocewrb/Kxjhe6zk2RXQ9AZiGDj3+4vXlj
# rbPe5LpWS9zyl3TwF11wJSZOx2yX+D8JgR2klAgniZsk4NFJq1sluIFutFuU3JgQ
# N5m8bR3yfe8ImKYXyu3mKSsAuoyLmM2RKrFzWLjOmgYn2JL4Glj0QWWznNWolNSQ
# jJBHszcEUtwrr3ls5SiLf+I+fXbxyicqREQsvrzyy7UbaJTv0y8S+Ofg2dcqGCTD
# qN89MZDHbxko+J7RnNUtNfb5glrqAvtwhx6B3T+qnyJQ/ExtGqy69tKBCAYKbCWV
# YnMBVg6oP2TgcX34mC9z6iR38W2GBPfCyYXNSD2FgRRD1Gy8jCkR/RQOwaF2YNY3
# q5AInqW1I0LuLhrPOg1tRUu9PeGlEqcHs4OmqKSgTgE9JchgWCJrCtgxdgaAXkMK
# LKZbpnyNni70H5hkIGXIxnw0mUUFIdWJQNMHZeTxfh99x7kuDfxhnaxS2oCgJhdi
# k7RhVQybBFrcwL/cxaywKRDc5oj4aS46qYm08nP8JQIIjIbszRA=
# =SOYX
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 30 Mar 2023 14:17:35 BST
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'misc-fixes-20230330' of https://github.com/philmd/qemu:
  block/dmg: Ignore C99 prototype declaration mismatch from <lzfse.h>
  hw/i2c: pmbus: block uninitialised string reads
  tests/avocado: Enable TuxRun/mips64 (big-endian) test
  hw/mips/gt64xxx_pci: Don't endian-swap GT_PCI0_CFGADDR
  linux-user/mips: Use P5600 as default CPU to run NaN2008 ELF binaries
  linux-user/sparc: Don't use 16-bit UIDs on SPARC V9

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

1 files changed, 6 insertions, 12 deletions

diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c
index f226d03420..82c15edb46 100644
--- a/hw/pci-host/gt64120.c
+++ b/hw/pci-host/gt64120.c
@@ -321,9 +321,6 @@ static void gt64120_isd_mapping(GT64120State *s)
 static void gt64120_update_pci_cfgdata_mapping(GT64120State *s)
 {
     /* Indexed on MByteSwap bit, see Table 158: PCI_0 Command, Offset: 0xc00 */
-    static const MemoryRegionOps *pci_host_conf_ops[] = {
-        &pci_host_conf_be_ops, &pci_host_conf_le_ops
-    };
     static const MemoryRegionOps *pci_host_data_ops[] = {
         &pci_host_data_be_ops, &pci_host_data_le_ops
     };
@@ -339,15 +336,6 @@ static void gt64120_update_pci_cfgdata_mapping(GT64120State *s)
      * - Table 16: 32-bit PCI Transaction Endianess
      * - Table 158: PCI_0 Command, Offset: 0xc00
      */
-    if (memory_region_is_mapped(&phb->conf_mem)) {
-        memory_region_del_subregion(&s->ISD_mem, &phb->conf_mem);
-        object_unparent(OBJECT(&phb->conf_mem));
-    }
-    memory_region_init_io(&phb->conf_mem, OBJECT(phb),
-                          pci_host_conf_ops[s->regs[GT_PCI0_CMD] & 1],
-                          s, "pci-conf-idx", 4);
-    memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGADDR << 2,
-                                        &phb->conf_mem, 1);
 
     if (memory_region_is_mapped(&phb->data_mem)) {
         memory_region_del_subregion(&s->ISD_mem, &phb->data_mem);
@@ -1208,6 +1196,12 @@ static void gt64120_realize(DeviceState *dev, Error **errp)
                                 PCI_DEVFN(18, 0), TYPE_PCI_BUS);
 
     pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
+    memory_region_init_io(&phb->conf_mem, OBJECT(phb),
+                          &pci_host_conf_le_ops,
+                          s, "pci-conf-idx", 4);
+    memory_region_add_subregion_overlap(&s->ISD_mem, GT_PCI0_CFGADDR << 2,
+                                        &phb->conf_mem, 1);
+
 
     /*
      * The whole address space decoded by the GT-64120A doesn't generate