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| author | Bharat Bhushan <r65777@freescale.com> | 2014-05-12 15:15:39 +0530 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-06-16 13:24:34 +0200 |
| commit | d575a6ce0efb96966240a53bf611ad6bf5a14ebd (patch) | |
| tree | f4bed306898675bebfbd6b32db0ea93819c857a9 /hw/pci-host/ppce500.c | |
| parent | 08215d8fd8ca15425401adc9e01361cbc6882402 (diff) | |
| download | focaccia-qemu-d575a6ce0efb96966240a53bf611ad6bf5a14ebd.tar.gz focaccia-qemu-d575a6ce0efb96966240a53bf611ad6bf5a14ebd.zip | |
PPC: e500: some pci related cleanup
- Use PCI_NUM_PINS rather than hardcoding - use "pin" wherever possible Signed-off-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'hw/pci-host/ppce500.c')
| -rw-r--r-- | hw/pci-host/ppce500.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c index e12d731ce8..242ba6f4c8 100644 --- a/hw/pci-host/ppce500.c +++ b/hw/pci-host/ppce500.c @@ -87,7 +87,7 @@ struct PPCE500PCIState { struct pci_outbound pob[PPCE500_PCI_NR_POBS]; struct pci_inbound pib[PPCE500_PCI_NR_PIBS]; uint32_t gasket_time; - qemu_irq irq[4]; + qemu_irq irq[PCI_NUM_PINS]; uint32_t first_slot; /* mmio maps */ MemoryRegion container; @@ -252,26 +252,26 @@ static const MemoryRegionOps e500_pci_reg_ops = { .endianness = DEVICE_BIG_ENDIAN, }; -static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num) +static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int pin) { int devno = pci_dev->devfn >> 3; int ret; - ret = ppce500_pci_map_irq_slot(devno, irq_num); + ret = ppce500_pci_map_irq_slot(devno, pin); pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__, - pci_dev->devfn, irq_num, ret, devno); + pci_dev->devfn, pin, ret, devno); return ret; } -static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level) +static void mpc85xx_pci_set_irq(void *opaque, int pin, int level) { qemu_irq *pic = opaque; - pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level); + pci_debug("%s: PCI irq %d, level:%d\n", __func__, pin , level); - qemu_set_irq(pic[irq_num], level); + qemu_set_irq(pic[pin], level); } static const VMStateDescription vmstate_pci_outbound = { |