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| author | Zhenzhong Duan <zhenzhong.duan@intel.com> | 2022-06-15 11:45:01 +0800 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2022-06-15 11:11:37 +0200 |
| commit | 766a9814749e35b1e4537f8a6ba71ab202ce5709 (patch) | |
| tree | fa602bb7f87d2cc43dddada597de63f0b9074cb6 /hw/pci-host/q35.c | |
| parent | aa4f3a3b880e9b2109e4b0baeb36cce3e1732159 (diff) | |
| download | focaccia-qemu-766a9814749e35b1e4537f8a6ba71ab202ce5709.tar.gz focaccia-qemu-766a9814749e35b1e4537f8a6ba71ab202ce5709.zip | |
q35：Enable TSEG only when G_SMRAME and TSEG_EN both enabled
According to spec: "TSEG Enable (T_EN): Enabling of SMRAM memory for Extended SMRAM space only. When G_SMRAME = 1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical address space. Note that once D_LCK is set, this bit becomes read only." Changed to match the spec description. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Message-Id: <20220615034501.2733802-1-zhenzhong.duan@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw/pci-host/q35.c')
| -rw-r--r-- | hw/pci-host/q35.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index ab5a47aff5..20da121374 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -379,7 +379,8 @@ static void mch_update_smram(MCHPCIState *mch) memory_region_set_enabled(&mch->high_smram, false); } - if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { + if ((pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) && + (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME)) { switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: |