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| author | Michael S. Tsirkin <mst@redhat.com> | 2012-02-21 15:49:01 +0200 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2012-03-16 00:41:39 +0200 |
| commit | 15ab7a75335108c76700bea67602017fe305350d (patch) | |
| tree | bb4f3ace224e6edce6bc23f1a20dd50678b9edb6 /hw/pci.c | |
| parent | 4eb812f7603f57dc63f6b74e3c464a60ed5bc91b (diff) | |
| download | focaccia-qemu-15ab7a75335108c76700bea67602017fe305350d.tar.gz focaccia-qemu-15ab7a75335108c76700bea67602017fe305350d.zip | |
pci: set memory type for memory behind the bridge
As we make upper bits in IO and prefetcheable memory registers writeable, we should declare support for 64 bit prefetcheable memory and 32 bit io in the bridge. This changes the default for apb, dec, but I'm guessing they got the defaults wrong by accident. Alternatively, we could let bridges declare lack of 64 bit support and make the upper bits read-only zero. Reported-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/pci.c')
| -rw-r--r-- | hw/pci.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/hw/pci.c b/hw/pci.c index 3ca5f4c820..fee27fcf87 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -663,8 +663,11 @@ static void pci_init_mask_bridge(PCIDevice *d) pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, PCI_BRIDGE_CTL_DISCARD_STATUS); d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; + d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, PCI_PREF_RANGE_TYPE_MASK); + pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, + PCI_PREF_RANGE_TYPE_MASK); } static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev) |