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| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-12-18 22:43:33 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-12-18 22:43:33 +0000 |
| commit | 8098ed414ada4265f646e94d65eca063b3689f50 (patch) | |
| tree | 4bcb312026eee379d04427b54edae8a42289f186 /hw/pci.c | |
| parent | 2231ef1084f1522508880e99ba60647f8d312c74 (diff) | |
| download | focaccia-qemu-8098ed414ada4265f646e94d65eca063b3689f50.tar.gz focaccia-qemu-8098ed414ada4265f646e94d65eca063b3689f50.zip | |
PCI: Mask writes to RO bits in the status reg of PCI config space
The Status register in the PCI config space has some read-only bits. Any writes to those bits should be masked out. Signed-off-by: Amit Shah <amit.shah@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6091 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/pci.c')
| -rw-r--r-- | hw/pci.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/hw/pci.c b/hw/pci.c index bf7db0db79..b95c79440c 100644 --- a/hw/pci.c +++ b/hw/pci.c @@ -381,6 +381,7 @@ void pci_default_write_config(PCIDevice *d, case 0x0b: case 0x0e: case 0x10 ... 0x27: /* base */ + case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */ case 0x30 ... 0x33: /* rom */ case 0x3d: can_write = 0; @@ -402,6 +403,7 @@ void pci_default_write_config(PCIDevice *d, case 0x0a: case 0x0b: case 0x0e: + case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */ case 0x38 ... 0x3b: /* rom */ case 0x3d: can_write = 0; @@ -413,6 +415,15 @@ void pci_default_write_config(PCIDevice *d, break; } if (can_write) { + /* Mask out writes to reserved bits in registers */ + switch (addr) { + case 0x06: + val &= ~PCI_STATUS_RESERVED_MASK_LO; + break; + case 0x07: + val &= ~PCI_STATUS_RESERVED_MASK_HI; + break; + } d->config[addr] = val; } if (++addr > 0xff) |