summary refs log tree commit diff stats
path: root/hw/pci.c
diff options
context:
space:
mode:
authorMichael S. Tsirkin <mst@redhat.com>2009-12-23 16:33:56 +0200
committerMichael S. Tsirkin <mst@redhat.com>2009-12-23 16:33:56 +0200
commita7b15a5cc6261629879d4d8a71bacf23f983000b (patch)
tree14ad658b875a38bc75ed9c7002257ec07b50abf6 /hw/pci.c
parent59d1c1c2d774cccb0a88ff73501f97bea190c154 (diff)
downloadfocaccia-qemu-a7b15a5cc6261629879d4d8a71bacf23f983000b.tar.gz
focaccia-qemu-a7b15a5cc6261629879d4d8a71bacf23f983000b.zip
Revert "Revert "pci: interrupt disable bit support""
This reverts commit d587e0787153f0224a6140c5015609963ceaabfb.
Diffstat (limited to 'hw/pci.c')
-rw-r--r--hw/pci.c29
1 files changed, 27 insertions, 2 deletions
diff --git a/hw/pci.c b/hw/pci.c
index 9cc5a6a3ef..d54f05ef22 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -521,7 +521,8 @@ static void pci_init_wmask(PCIDevice *dev)
     dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
     dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
     pci_set_word(dev->wmask + PCI_COMMAND,
-                 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+                 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
+                 PCI_COMMAND_INTX_DISABLE);
 
     memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
            config_size - PCI_CONFIG_HEADER_SIZE);
@@ -946,6 +947,25 @@ static void pci_update_mappings(PCIDevice *d)
     }
 }
 
+static inline int pci_irq_disabled(PCIDevice *d)
+{
+    return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
+}
+
+/* Called after interrupt disabled field update in config space,
+ * assert/deassert interrupts if necessary.
+ * Gets original interrupt disable bit value (before update). */
+static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
+{
+    int i, disabled = pci_irq_disabled(d);
+    if (disabled == was_irq_disabled)
+        return;
+    for (i = 0; i < PCI_NUM_PINS; ++i) {
+        int state = pci_irq_state(d, i);
+        pci_change_irq_level(d, i, disabled ? -state : state);
+    }
+}
+
 uint32_t pci_default_read_config(PCIDevice *d,
                                  uint32_t address, int len)
 {
@@ -958,7 +978,7 @@ uint32_t pci_default_read_config(PCIDevice *d,
 
 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 {
-    int i;
+    int i, was_irq_disabled = pci_irq_disabled(d);
     uint32_t config_size = pci_config_size(d);
 
     for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
@@ -970,6 +990,9 @@ void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
         ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
         range_covers_byte(addr, l, PCI_COMMAND))
         pci_update_mappings(d);
+
+    if (range_covers_byte(addr, l, PCI_COMMAND))
+        pci_update_irq_disabled(d, was_irq_disabled);
 }
 
 /***********************************************************/
@@ -987,6 +1010,8 @@ static void pci_set_irq(void *opaque, int irq_num, int level)
 
     pci_set_irq_state(pci_dev, irq_num, level);
     pci_update_irq_status(pci_dev);
+    if (pci_irq_disabled(pci_dev))
+        return;
     pci_change_irq_level(pci_dev, irq_num, change);
 }