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| author | Michael S. Tsirkin <mst@redhat.com> | 2023-08-29 16:14:29 -0400 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2023-10-04 04:53:52 -0400 |
| commit | 4565917bb034479a29c04f0b44124e7f61585ccf (patch) | |
| tree | fe087c680bd572a2fdeafa343876177705ad0fdc /hw/pci/pci.c | |
| parent | 494a6a2cf7f775d2c20fd6df9601e30606cc2014 (diff) | |
| download | focaccia-qemu-4565917bb034479a29c04f0b44124e7f61585ccf.tar.gz focaccia-qemu-4565917bb034479a29c04f0b44124e7f61585ccf.zip | |
pci: SLT must be RO
current code sets PCI_SEC_LATENCY_TIMER to RW, but for
pcie to pcie bridges it must be RO 0 according to
pci express spec which says:
This register does not apply to PCI Express. It must be read-only
and hardwired to 00h. For PCI Express to PCI/PCI-X Bridges, refer to the
[PCIe-to-PCI-PCI-X-Bridge] for requirements for this register.
also, fix typo in comment where it's made writeable - this typo
is likely what prevented us noticing we violate this requirement
in the 1st place.
Reported-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Message-Id: <de9d05366a70172e1789d10591dbe59e39c3849c.1693432039.git.mst@redhat.com>
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/pci/pci.c')
| -rw-r--r-- | hw/pci/pci.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 881d774fb6..b0d21bf43a 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -893,7 +893,7 @@ static void pci_init_w1cmask(PCIDevice *dev) static void pci_init_mask_bridge(PCIDevice *d) { /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and - PCI_SEC_LETENCY_TIMER */ + PCI_SEC_LATENCY_TIMER */ memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); /* base and limit */ |