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authorMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>2017-09-22 13:18:31 +0100
committerMichael S. Tsirkin <mst@redhat.com>2017-10-15 05:54:41 +0300
commit9cd1e97a7ae2856ec00b5682db0dea17f42fc734 (patch)
treedbce61b3f443624c8808da1b6ea8f84fac0d73c8 /hw/pci/pci_bridge.c
parent5c0ba1be37181bd8a7c96c7f81b19ae5f8e66e2d (diff)
downloadfocaccia-qemu-9cd1e97a7ae2856ec00b5682db0dea17f42fc734.tar.gz
focaccia-qemu-9cd1e97a7ae2856ec00b5682db0dea17f42fc734.zip
pci: allow 32-bit PCI IO accesses to pass through the PCI bridge
Whilst the underlying PCI bridge implementation supports 32-bit PCI IO
accesses, unfortunately they are truncated at the legacy 64K limit.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'hw/pci/pci_bridge.c')
-rw-r--r--hw/pci/pci_bridge.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c
index 17feae5ed8..a47d257149 100644
--- a/hw/pci/pci_bridge.c
+++ b/hw/pci/pci_bridge.c
@@ -379,7 +379,8 @@ void pci_bridge_initfn(PCIDevice *dev, const char *typename)
     sec_bus->address_space_mem = &br->address_space_mem;
     memory_region_init(&br->address_space_mem, OBJECT(br), "pci_bridge_pci", UINT64_MAX);
     sec_bus->address_space_io = &br->address_space_io;
-    memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io", 65536);
+    memory_region_init(&br->address_space_io, OBJECT(br), "pci_bridge_io",
+                       UINT32_MAX);
     br->windows = pci_bridge_region_init(br);
     QLIST_INIT(&sec_bus->child);
     QLIST_INSERT_HEAD(&parent->child, sec_bus, sibling);