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authorpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2008-07-02 16:48:32 +0000
committerpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2008-07-02 16:48:32 +0000
commit23e39294034e13d29a0707483542bab850d601b4 (patch)
treebf8c1fa3e39234083a06bd7b579476f870853b06 /hw/pl011.c
parentab19b0ecfddf94ae2053b973cea5a58c8dac0363 (diff)
downloadfocaccia-qemu-23e39294034e13d29a0707483542bab850d601b4.tar.gz
focaccia-qemu-23e39294034e13d29a0707483542bab850d601b4.zip
Save/restore for stellaris boards.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4824 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/pl011.c')
-rw-r--r--hw/pl011.c53
1 files changed, 52 insertions, 1 deletions
diff --git a/hw/pl011.c b/hw/pl011.c
index 6676644991..bbef0a4c6d 100644
--- a/hw/pl011.c
+++ b/hw/pl011.c
@@ -238,6 +238,57 @@ static CPUWriteMemoryFunc *pl011_writefn[] = {
    pl011_write
 };
 
+static void pl011_save(QEMUFile *f, void *opaque)
+{
+    pl011_state *s = (pl011_state *)opaque;
+    int i;
+
+    qemu_put_be32(f, s->readbuff);
+    qemu_put_be32(f, s->flags);
+    qemu_put_be32(f, s->lcr);
+    qemu_put_be32(f, s->cr);
+    qemu_put_be32(f, s->dmacr);
+    qemu_put_be32(f, s->int_enabled);
+    qemu_put_be32(f, s->int_level);
+    for (i = 0; i < 16; i++)
+        qemu_put_be32(f, s->read_fifo[i]);
+    qemu_put_be32(f, s->ilpr);
+    qemu_put_be32(f, s->ibrd);
+    qemu_put_be32(f, s->fbrd);
+    qemu_put_be32(f, s->ifl);
+    qemu_put_be32(f, s->read_pos);
+    qemu_put_be32(f, s->read_count);
+    qemu_put_be32(f, s->read_trigger);
+}
+
+static int pl011_load(QEMUFile *f, void *opaque, int version_id)
+{
+    pl011_state *s = (pl011_state *)opaque;
+    int i;
+
+    if (version_id != 1)
+        return -EINVAL;
+
+    s->readbuff = qemu_get_be32(f);
+    s->flags = qemu_get_be32(f);
+    s->lcr = qemu_get_be32(f);
+    s->cr = qemu_get_be32(f);
+    s->dmacr = qemu_get_be32(f);
+    s->int_enabled = qemu_get_be32(f);
+    s->int_level = qemu_get_be32(f);
+    for (i = 0; i < 16; i++)
+        s->read_fifo[i] = qemu_get_be32(f);
+    s->ilpr = qemu_get_be32(f);
+    s->ibrd = qemu_get_be32(f);
+    s->fbrd = qemu_get_be32(f);
+    s->ifl = qemu_get_be32(f);
+    s->read_pos = qemu_get_be32(f);
+    s->read_count = qemu_get_be32(f);
+    s->read_trigger = qemu_get_be32(f);
+
+    return 0;
+}
+
 void pl011_init(uint32_t base, qemu_irq irq,
                 CharDriverState *chr, enum pl011_type type)
 {
@@ -260,6 +311,6 @@ void pl011_init(uint32_t base, qemu_irq irq,
         qemu_chr_add_handlers(chr, pl011_can_receive, pl011_receive,
                               pl011_event, s);
     }
-    /* ??? Save/restore.  */
+    register_savevm("pl011_uart", -1, 1, pl011_save, pl011_load, s);
 }