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| author | Alexander Graf <agraf@suse.de> | 2012-10-08 12:21:30 +0200 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2012-10-29 11:45:56 +0100 |
| commit | a1bc20dfbb012ea2a5fb1228cb77abd04490fd79 (patch) | |
| tree | 9ef704599b65f54a1e7e9703b2dab16f08f470c0 /hw/ppc/e500.c | |
| parent | 626c7a171e644fbe1579516b8b794d611c295d2f (diff) | |
| download | focaccia-qemu-a1bc20dfbb012ea2a5fb1228cb77abd04490fd79.tar.gz focaccia-qemu-a1bc20dfbb012ea2a5fb1228cb77abd04490fd79.zip | |
PPC: e500: Map PIO space into core memory region
On PPC, we don't have PIO. So usually PIO space behind a PCI bridge is accessible via MMIO. Do this mapping explicitly by mapping the PIO space of our PCI bus into a memory region that lives in memory space. Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'hw/ppc/e500.c')
| -rw-r--r-- | hw/ppc/e500.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 90d88ebc74..6749ffffb3 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -52,7 +52,6 @@ #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000ULL) #define MPC8544_PCI_REGS_SIZE 0x1000ULL #define MPC8544_PCI_IO 0xE1000000ULL -#define MPC8544_PCI_IOLEN 0x10000ULL #define MPC8544_UTIL_BASE (MPC8544_CCSRBAR_BASE + 0xe0000ULL) #define MPC8544_SPIN_BASE 0xEF000000ULL @@ -511,7 +510,7 @@ void ppce500_init(PPCE500Params *params) if (!pci_bus) printf("couldn't create PCI controller!\n"); - isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN); + sysbus_mmio_map(sysbus_from_qdev(dev), 1, MPC8544_PCI_IO); if (pci_bus) { /* Register network interfaces. */ |