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| author | Caleb Schlossin <calebs@linux.vnet.ibm.com> | 2024-02-27 14:36:23 -0600 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2024-03-13 02:47:04 +1000 |
| commit | 9940412ae4ae2d4971959c13311ba8d822974452 (patch) | |
| tree | aeeea6c94ebb348eaa93b57838d40371099cee3f /hw/ppc/pnv_core.c | |
| parent | 0b8893236ef11dd26be9290156ea34cb122e4dbe (diff) | |
| download | focaccia-qemu-9940412ae4ae2d4971959c13311ba8d822974452.tar.gz focaccia-qemu-9940412ae4ae2d4971959c13311ba8d822974452.zip | |
ppc/pnv: Improve pervasive topology calculation for big-core
Big (SMT8) cores have a complicated function to map the core, thread ID to pervasive topology (PIR). Fix this for power8, power9, and power10. Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Caleb Schlossin <calebs@linux.vnet.ibm.com> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'hw/ppc/pnv_core.c')
| -rw-r--r-- | hw/ppc/pnv_core.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 8c7afe037f..f40ab721d6 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -226,7 +226,7 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp, int thread_index) { CPUPPCState *env = &cpu->env; - int core_pir; + int core_hwid; ppc_spr_t *pir = &env->spr_cb[SPR_PIR]; ppc_spr_t *tir = &env->spr_cb[SPR_TIR]; Error *local_err = NULL; @@ -242,10 +242,10 @@ static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp, return; } - core_pir = object_property_get_uint(OBJECT(pc), "pir", &error_abort); + core_hwid = object_property_get_uint(OBJECT(pc), "hwid", &error_abort); tir->default_value = thread_index; - pir->default_value = core_pir + thread_index; + pir->default_value = pcc->chip_pir(pc->chip, core_hwid, thread_index); /* Set time-base frequency to 512 MHz */ cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); @@ -342,7 +342,7 @@ static void pnv_core_unrealize(DeviceState *dev) } static Property pnv_core_properties[] = { - DEFINE_PROP_UINT32("pir", PnvCore, pir, 0), + DEFINE_PROP_UINT32("hwid", PnvCore, hwid, 0), DEFINE_PROP_UINT64("hrmor", PnvCore, hrmor, 0), DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *), DEFINE_PROP_END_OF_LIST(), |