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| author | Nicholas Piggin <npiggin@gmail.com> | 2020-03-17 00:26:08 +1000 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2020-03-17 17:00:22 +1100 |
| commit | edfdbf9c6baf6f8dc17842bd300cd2dd78d5f0d4 (patch) | |
| tree | c5a318e2c79846af0fddc4e271dc51dcbb605ba7 /hw/ppc | |
| parent | 8af7e1fe6fa4bdd3c4561c13a4bd4ee525e6f02f (diff) | |
| download | focaccia-qemu-edfdbf9c6baf6f8dc17842bd300cd2dd78d5f0d4.tar.gz focaccia-qemu-edfdbf9c6baf6f8dc17842bd300cd2dd78d5f0d4.zip | |
ppc/spapr: Add FWNMI System Reset state
The FWNMI option must deliver system reset interrupts to their registered address, and there are a few constraints on the handler addresses specified in PAPR. Add the system reset address state and checks. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Message-Id: <20200316142613.121089-4-npiggin@gmail.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviwed-by: Mahesh Salgaonkar <mahesh@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/ppc')
| -rw-r--r-- | hw/ppc/spapr.c | 2 | ||||
| -rw-r--r-- | hw/ppc/spapr_rtas.c | 14 |
2 files changed, 15 insertions, 1 deletions
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 822dea8118..d22bf54baf 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1688,6 +1688,7 @@ static void spapr_machine_reset(MachineState *machine) spapr->cas_reboot = false; + spapr->fwnmi_system_reset_addr = -1; spapr->fwnmi_machine_check_addr = -1; spapr->fwnmi_machine_check_interlock = -1; @@ -2007,6 +2008,7 @@ static const VMStateDescription vmstate_spapr_fwnmi = { .needed = spapr_fwnmi_needed, .pre_save = spapr_fwnmi_pre_save, .fields = (VMStateField[]) { + VMSTATE_UINT64(fwnmi_system_reset_addr, SpaprMachineState), VMSTATE_UINT64(fwnmi_machine_check_addr, SpaprMachineState), VMSTATE_INT32(fwnmi_machine_check_interlock, SpaprMachineState), VMSTATE_END_OF_LIST() diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 0b8c481593..521e6b0b72 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -414,6 +414,7 @@ static void rtas_ibm_nmi_register(PowerPCCPU *cpu, uint32_t nret, target_ulong rets) { hwaddr rtas_addr; + target_ulong sreset_addr, mce_addr; if (spapr_get_cap(spapr, SPAPR_CAP_FWNMI) == SPAPR_CAP_OFF) { rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); @@ -426,7 +427,18 @@ static void rtas_ibm_nmi_register(PowerPCCPU *cpu, return; } - spapr->fwnmi_machine_check_addr = rtas_ld(args, 1); + sreset_addr = rtas_ld(args, 0); + mce_addr = rtas_ld(args, 1); + + /* PAPR requires these are in the first 32M of memory and within RMA */ + if (sreset_addr >= 32 * MiB || sreset_addr >= spapr->rma_size || + mce_addr >= 32 * MiB || mce_addr >= spapr->rma_size) { + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); + return; + } + + spapr->fwnmi_system_reset_addr = sreset_addr; + spapr->fwnmi_machine_check_addr = mce_addr; rtas_st(rets, 0, RTAS_OUT_SUCCESS); } |