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authorAndreas Färber <afaerber@suse.de>2012-12-17 06:18:02 +0100
committerAndreas Färber <afaerber@suse.de>2013-01-15 04:09:13 +0100
commit55e5c2850293547203874098f7cec148ffd12dfa (patch)
treef9a9cc316999b7b52726b5186a925022b3747daa /hw/pxa2xx_gpio.c
parent1b1ed8dc40635d60dd95c04658989af63542fcbf (diff)
downloadfocaccia-qemu-55e5c2850293547203874098f7cec148ffd12dfa.tar.gz
focaccia-qemu-55e5c2850293547203874098f7cec148ffd12dfa.zip
cpu: Move cpu_index field to CPUState
Note that target-alpha accesses this field from TCG, now using a
negative offset. Therefore the field is placed last in CPUState.

Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change.

Move common parts of mips cpu_state_reset() to mips_cpu_reset().

Acked-by: Richard Henderson <rth@twiddle.net> (for alpha)
[AF: Rebased onto ppc CPU subclasses and openpic changes]
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'hw/pxa2xx_gpio.c')
-rw-r--r--hw/pxa2xx_gpio.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c
index 016833dfa1..c02c295af4 100644
--- a/hw/pxa2xx_gpio.c
+++ b/hw/pxa2xx_gpio.c
@@ -250,13 +250,14 @@ static const MemoryRegionOps pxa_gpio_ops = {
 };
 
 DeviceState *pxa2xx_gpio_init(hwaddr base,
-                CPUARMState *env, DeviceState *pic, int lines)
+                              ARMCPU *cpu, DeviceState *pic, int lines)
 {
+    CPUState *cs = CPU(cpu);
     DeviceState *dev;
 
     dev = qdev_create(NULL, "pxa2xx-gpio");
     qdev_prop_set_int32(dev, "lines", lines);
-    qdev_prop_set_int32(dev, "ncpu", env->cpu_index);
+    qdev_prop_set_int32(dev, "ncpu", cs->cpu_index);
     qdev_init_nofail(dev);
 
     sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);