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| author | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-17 18:43:47 +0000 |
|---|---|---|
| committer | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-17 18:43:47 +0000 |
| commit | e1dad5a615fb4a2d5cd43cbc0fc42f6a0d35f2e9 (patch) | |
| tree | 683799618318bd70cc7505aa14d604ff164c0c01 /hw/pxa2xx_gpio.c | |
| parent | 749bc4bf0bcd36e38b86d75a98f287f1941394cb (diff) | |
| download | focaccia-qemu-e1dad5a615fb4a2d5cd43cbc0fc42f6a0d35f2e9.tar.gz focaccia-qemu-e1dad5a615fb4a2d5cd43cbc0fc42f6a0d35f2e9.zip | |
Better STOPINTR bit semantics in the PXA2xx DMA.
Don't error out on reading GPCR register, just warn (Thorsten Zitterell). Don't zero a memory that's already zeroed. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3676 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/pxa2xx_gpio.c')
| -rw-r--r-- | hw/pxa2xx_gpio.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c index 9f5184438c..e3a30bc45e 100644 --- a/hw/pxa2xx_gpio.c +++ b/hw/pxa2xx_gpio.c @@ -154,6 +154,11 @@ static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset) __FUNCTION__, offset); return s->gpsr[bank]; /* Return last written value. */ + case GPCR: /* GPIO Pin-Output Clear registers */ + printf("%s: Read from a write-only register " REG_FMT "\n", + __FUNCTION__, offset); + return 31337; /* Specified as unpredictable in the docs. */ + case GRER: /* GPIO Rising-Edge Detect Enable registers */ return s->rising[bank]; |